1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_OMU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_OMU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_OMU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_OMU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- OMU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup OMU_Peripheral_Access_Layer OMU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** OMU - Size of Registers Arrays */ 72 #define OMU_ZONE_REGS_COUNT 4u 73 #define OMU_OVERLAY_REGION_DESCRIPTOR_COUNT 64u 74 75 /** OMU - Register Layout Typedef */ 76 typedef struct { 77 struct OMU_ZONE_REGS { /* offset: 0x0, array step: 0x1000 */ 78 __I uint32_t ZZRSR; /**< Zone Request Status 0..Zone Request Status 3, array offset: 0x0, array step: 0x1000 */ 79 __IO uint32_t ZER; /**< Zone Enable 0..Zone Enable 3, array offset: 0x4, array step: 0x1000 */ 80 uint8_t RESERVED_0[4088]; 81 } ZONE_REGS[OMU_ZONE_REGS_COUNT]; 82 __IO uint32_t OER; /**< OMU Enable, offset: 0x4000 */ 83 __IO uint32_t ZRR; /**< Zone Request, offset: 0x4004 */ 84 __I uint32_t ZESR; /**< Zone Enable Status, offset: 0x4008 */ 85 uint8_t RESERVED_0[1012]; 86 struct OMU_OVERLAY_REGION_DESCRIPTOR { /* offset: 0x4400, array step: 0x10 */ 87 __IO uint32_t ORDLSA; /**< ORD0 Logical Start Address..ORD63 Logical Start Address, array offset: 0x4400, array step: 0x10 */ 88 __IO uint32_t ORDPSA; /**< ORD0 Physical Start Address..ORD63 Physical Start Address, array offset: 0x4404, array step: 0x10 */ 89 __IO uint32_t ORDRS; /**< ORD0 Region Size..ORD63 Region Size, array offset: 0x4408, array step: 0x10 */ 90 __IO uint32_t ORDRZA; /**< ORD0 Region Zone Assignment..ORD63 Region Zone Assignment, array offset: 0x440C, array step: 0x10 */ 91 } OVERLAY_REGION_DESCRIPTOR[OMU_OVERLAY_REGION_DESCRIPTOR_COUNT]; 92 } OMU_Type, *OMU_MemMapPtr; 93 94 /** Number of instances of the OMU module. */ 95 #define OMU_INSTANCE_COUNT (2u) 96 97 /* OMU - Peripheral instance base addresses */ 98 /** Peripheral RTU0__OMU base address */ 99 #define IP_RTU0__OMU_BASE (0x761A0000u) 100 /** Peripheral RTU0__OMU base pointer */ 101 #define IP_RTU0__OMU ((OMU_Type *)IP_RTU0__OMU_BASE) 102 /** Peripheral RTU1__OMU base address */ 103 #define IP_RTU1__OMU_BASE (0x769A0000u) 104 /** Peripheral RTU1__OMU base pointer */ 105 #define IP_RTU1__OMU ((OMU_Type *)IP_RTU1__OMU_BASE) 106 /** Array initializer of OMU peripheral base addresses */ 107 #define IP_OMU_BASE_ADDRS { IP_RTU0__OMU_BASE, IP_RTU1__OMU_BASE } 108 /** Array initializer of OMU peripheral base pointers */ 109 #define IP_OMU_BASE_PTRS { IP_RTU0__OMU, IP_RTU1__OMU } 110 111 /* ---------------------------------------------------------------------------- 112 -- OMU Register Masks 113 ---------------------------------------------------------------------------- */ 114 115 /*! 116 * @addtogroup OMU_Register_Masks OMU Register Masks 117 * @{ 118 */ 119 120 /*! @name ZZRSR - Zone Request Status 0..Zone Request Status 3 */ 121 /*! @{ */ 122 123 #define OMU_ZZRSR_Z0RS_MASK (0x1U) 124 #define OMU_ZZRSR_Z0RS_SHIFT (0U) 125 #define OMU_ZZRSR_Z0RS_WIDTH (1U) 126 #define OMU_ZZRSR_Z0RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z0RS_SHIFT)) & OMU_ZZRSR_Z0RS_MASK) 127 128 #define OMU_ZZRSR_Z2RS_MASK (0x1U) 129 #define OMU_ZZRSR_Z2RS_SHIFT (0U) 130 #define OMU_ZZRSR_Z2RS_WIDTH (1U) 131 #define OMU_ZZRSR_Z2RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z2RS_SHIFT)) & OMU_ZZRSR_Z2RS_MASK) 132 133 #define OMU_ZZRSR_Z4RS_MASK (0x1U) 134 #define OMU_ZZRSR_Z4RS_SHIFT (0U) 135 #define OMU_ZZRSR_Z4RS_WIDTH (1U) 136 #define OMU_ZZRSR_Z4RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z4RS_SHIFT)) & OMU_ZZRSR_Z4RS_MASK) 137 138 #define OMU_ZZRSR_Z6RS_MASK (0x1U) 139 #define OMU_ZZRSR_Z6RS_SHIFT (0U) 140 #define OMU_ZZRSR_Z6RS_WIDTH (1U) 141 #define OMU_ZZRSR_Z6RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z6RS_SHIFT)) & OMU_ZZRSR_Z6RS_MASK) 142 143 #define OMU_ZZRSR_Z1RS_MASK (0x2U) 144 #define OMU_ZZRSR_Z1RS_SHIFT (1U) 145 #define OMU_ZZRSR_Z1RS_WIDTH (1U) 146 #define OMU_ZZRSR_Z1RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z1RS_SHIFT)) & OMU_ZZRSR_Z1RS_MASK) 147 148 #define OMU_ZZRSR_Z3RS_MASK (0x2U) 149 #define OMU_ZZRSR_Z3RS_SHIFT (1U) 150 #define OMU_ZZRSR_Z3RS_WIDTH (1U) 151 #define OMU_ZZRSR_Z3RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z3RS_SHIFT)) & OMU_ZZRSR_Z3RS_MASK) 152 153 #define OMU_ZZRSR_Z5RS_MASK (0x2U) 154 #define OMU_ZZRSR_Z5RS_SHIFT (1U) 155 #define OMU_ZZRSR_Z5RS_WIDTH (1U) 156 #define OMU_ZZRSR_Z5RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z5RS_SHIFT)) & OMU_ZZRSR_Z5RS_MASK) 157 158 #define OMU_ZZRSR_Z7RS_MASK (0x2U) 159 #define OMU_ZZRSR_Z7RS_SHIFT (1U) 160 #define OMU_ZZRSR_Z7RS_WIDTH (1U) 161 #define OMU_ZZRSR_Z7RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZZRSR_Z7RS_SHIFT)) & OMU_ZZRSR_Z7RS_MASK) 162 /*! @} */ 163 164 /*! @name ZER - Zone Enable 0..Zone Enable 3 */ 165 /*! @{ */ 166 167 #define OMU_ZER_Z0E_MASK (0x1U) 168 #define OMU_ZER_Z0E_SHIFT (0U) 169 #define OMU_ZER_Z0E_WIDTH (1U) 170 #define OMU_ZER_Z0E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z0E_SHIFT)) & OMU_ZER_Z0E_MASK) 171 172 #define OMU_ZER_Z2E_MASK (0x1U) 173 #define OMU_ZER_Z2E_SHIFT (0U) 174 #define OMU_ZER_Z2E_WIDTH (1U) 175 #define OMU_ZER_Z2E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z2E_SHIFT)) & OMU_ZER_Z2E_MASK) 176 177 #define OMU_ZER_Z4E_MASK (0x1U) 178 #define OMU_ZER_Z4E_SHIFT (0U) 179 #define OMU_ZER_Z4E_WIDTH (1U) 180 #define OMU_ZER_Z4E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z4E_SHIFT)) & OMU_ZER_Z4E_MASK) 181 182 #define OMU_ZER_Z6E_MASK (0x1U) 183 #define OMU_ZER_Z6E_SHIFT (0U) 184 #define OMU_ZER_Z6E_WIDTH (1U) 185 #define OMU_ZER_Z6E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z6E_SHIFT)) & OMU_ZER_Z6E_MASK) 186 187 #define OMU_ZER_Z1E_MASK (0x2U) 188 #define OMU_ZER_Z1E_SHIFT (1U) 189 #define OMU_ZER_Z1E_WIDTH (1U) 190 #define OMU_ZER_Z1E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z1E_SHIFT)) & OMU_ZER_Z1E_MASK) 191 192 #define OMU_ZER_Z3E_MASK (0x2U) 193 #define OMU_ZER_Z3E_SHIFT (1U) 194 #define OMU_ZER_Z3E_WIDTH (1U) 195 #define OMU_ZER_Z3E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z3E_SHIFT)) & OMU_ZER_Z3E_MASK) 196 197 #define OMU_ZER_Z5E_MASK (0x2U) 198 #define OMU_ZER_Z5E_SHIFT (1U) 199 #define OMU_ZER_Z5E_WIDTH (1U) 200 #define OMU_ZER_Z5E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z5E_SHIFT)) & OMU_ZER_Z5E_MASK) 201 202 #define OMU_ZER_Z7E_MASK (0x2U) 203 #define OMU_ZER_Z7E_SHIFT (1U) 204 #define OMU_ZER_Z7E_WIDTH (1U) 205 #define OMU_ZER_Z7E(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZER_Z7E_SHIFT)) & OMU_ZER_Z7E_MASK) 206 /*! @} */ 207 208 /*! @name OER - OMU Enable */ 209 /*! @{ */ 210 211 #define OMU_OER_OE_MASK (0x1U) 212 #define OMU_OER_OE_SHIFT (0U) 213 #define OMU_OER_OE_WIDTH (1U) 214 #define OMU_OER_OE(x) (((uint32_t)(((uint32_t)(x)) << OMU_OER_OE_SHIFT)) & OMU_OER_OE_MASK) 215 /*! @} */ 216 217 /*! @name ZRR - Zone Request */ 218 /*! @{ */ 219 220 #define OMU_ZRR_Z0R_MASK (0x1U) 221 #define OMU_ZRR_Z0R_SHIFT (0U) 222 #define OMU_ZRR_Z0R_WIDTH (1U) 223 #define OMU_ZRR_Z0R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z0R_SHIFT)) & OMU_ZRR_Z0R_MASK) 224 225 #define OMU_ZRR_Z1R_MASK (0x2U) 226 #define OMU_ZRR_Z1R_SHIFT (1U) 227 #define OMU_ZRR_Z1R_WIDTH (1U) 228 #define OMU_ZRR_Z1R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z1R_SHIFT)) & OMU_ZRR_Z1R_MASK) 229 230 #define OMU_ZRR_Z2R_MASK (0x4U) 231 #define OMU_ZRR_Z2R_SHIFT (2U) 232 #define OMU_ZRR_Z2R_WIDTH (1U) 233 #define OMU_ZRR_Z2R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z2R_SHIFT)) & OMU_ZRR_Z2R_MASK) 234 235 #define OMU_ZRR_Z3R_MASK (0x8U) 236 #define OMU_ZRR_Z3R_SHIFT (3U) 237 #define OMU_ZRR_Z3R_WIDTH (1U) 238 #define OMU_ZRR_Z3R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z3R_SHIFT)) & OMU_ZRR_Z3R_MASK) 239 240 #define OMU_ZRR_Z4R_MASK (0x10U) 241 #define OMU_ZRR_Z4R_SHIFT (4U) 242 #define OMU_ZRR_Z4R_WIDTH (1U) 243 #define OMU_ZRR_Z4R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z4R_SHIFT)) & OMU_ZRR_Z4R_MASK) 244 245 #define OMU_ZRR_Z5R_MASK (0x20U) 246 #define OMU_ZRR_Z5R_SHIFT (5U) 247 #define OMU_ZRR_Z5R_WIDTH (1U) 248 #define OMU_ZRR_Z5R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z5R_SHIFT)) & OMU_ZRR_Z5R_MASK) 249 250 #define OMU_ZRR_Z6R_MASK (0x40U) 251 #define OMU_ZRR_Z6R_SHIFT (6U) 252 #define OMU_ZRR_Z6R_WIDTH (1U) 253 #define OMU_ZRR_Z6R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z6R_SHIFT)) & OMU_ZRR_Z6R_MASK) 254 255 #define OMU_ZRR_Z7R_MASK (0x80U) 256 #define OMU_ZRR_Z7R_SHIFT (7U) 257 #define OMU_ZRR_Z7R_WIDTH (1U) 258 #define OMU_ZRR_Z7R(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZRR_Z7R_SHIFT)) & OMU_ZRR_Z7R_MASK) 259 /*! @} */ 260 261 /*! @name ZESR - Zone Enable Status */ 262 /*! @{ */ 263 264 #define OMU_ZESR_Z0ES_MASK (0x1U) 265 #define OMU_ZESR_Z0ES_SHIFT (0U) 266 #define OMU_ZESR_Z0ES_WIDTH (1U) 267 #define OMU_ZESR_Z0ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z0ES_SHIFT)) & OMU_ZESR_Z0ES_MASK) 268 269 #define OMU_ZESR_Z1ES_MASK (0x2U) 270 #define OMU_ZESR_Z1ES_SHIFT (1U) 271 #define OMU_ZESR_Z1ES_WIDTH (1U) 272 #define OMU_ZESR_Z1ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z1ES_SHIFT)) & OMU_ZESR_Z1ES_MASK) 273 274 #define OMU_ZESR_Z2ES_MASK (0x4U) 275 #define OMU_ZESR_Z2ES_SHIFT (2U) 276 #define OMU_ZESR_Z2ES_WIDTH (1U) 277 #define OMU_ZESR_Z2ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z2ES_SHIFT)) & OMU_ZESR_Z2ES_MASK) 278 279 #define OMU_ZESR_Z3ES_MASK (0x8U) 280 #define OMU_ZESR_Z3ES_SHIFT (3U) 281 #define OMU_ZESR_Z3ES_WIDTH (1U) 282 #define OMU_ZESR_Z3ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z3ES_SHIFT)) & OMU_ZESR_Z3ES_MASK) 283 284 #define OMU_ZESR_Z4ES_MASK (0x10U) 285 #define OMU_ZESR_Z4ES_SHIFT (4U) 286 #define OMU_ZESR_Z4ES_WIDTH (1U) 287 #define OMU_ZESR_Z4ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z4ES_SHIFT)) & OMU_ZESR_Z4ES_MASK) 288 289 #define OMU_ZESR_Z5ES_MASK (0x20U) 290 #define OMU_ZESR_Z5ES_SHIFT (5U) 291 #define OMU_ZESR_Z5ES_WIDTH (1U) 292 #define OMU_ZESR_Z5ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z5ES_SHIFT)) & OMU_ZESR_Z5ES_MASK) 293 294 #define OMU_ZESR_Z6ES_MASK (0x40U) 295 #define OMU_ZESR_Z6ES_SHIFT (6U) 296 #define OMU_ZESR_Z6ES_WIDTH (1U) 297 #define OMU_ZESR_Z6ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z6ES_SHIFT)) & OMU_ZESR_Z6ES_MASK) 298 299 #define OMU_ZESR_Z7ES_MASK (0x80U) 300 #define OMU_ZESR_Z7ES_SHIFT (7U) 301 #define OMU_ZESR_Z7ES_WIDTH (1U) 302 #define OMU_ZESR_Z7ES(x) (((uint32_t)(((uint32_t)(x)) << OMU_ZESR_Z7ES_SHIFT)) & OMU_ZESR_Z7ES_MASK) 303 /*! @} */ 304 305 /*! @name ORDLSA - ORD0 Logical Start Address..ORD63 Logical Start Address */ 306 /*! @{ */ 307 308 #define OMU_ORDLSA_LSA_MASK (0xFFFFFC00U) 309 #define OMU_ORDLSA_LSA_SHIFT (10U) 310 #define OMU_ORDLSA_LSA_WIDTH (22U) 311 #define OMU_ORDLSA_LSA(x) (((uint32_t)(((uint32_t)(x)) << OMU_ORDLSA_LSA_SHIFT)) & OMU_ORDLSA_LSA_MASK) 312 /*! @} */ 313 314 /*! @name ORDPSA - ORD0 Physical Start Address..ORD63 Physical Start Address */ 315 /*! @{ */ 316 317 #define OMU_ORDPSA_PSA_MASK (0xFFFFFC00U) 318 #define OMU_ORDPSA_PSA_SHIFT (10U) 319 #define OMU_ORDPSA_PSA_WIDTH (22U) 320 #define OMU_ORDPSA_PSA(x) (((uint32_t)(((uint32_t)(x)) << OMU_ORDPSA_PSA_SHIFT)) & OMU_ORDPSA_PSA_MASK) 321 /*! @} */ 322 323 /*! @name ORDRS - ORD0 Region Size..ORD63 Region Size */ 324 /*! @{ */ 325 326 #define OMU_ORDRS_RS_MASK (0xFU) 327 #define OMU_ORDRS_RS_SHIFT (0U) 328 #define OMU_ORDRS_RS_WIDTH (4U) 329 #define OMU_ORDRS_RS(x) (((uint32_t)(((uint32_t)(x)) << OMU_ORDRS_RS_SHIFT)) & OMU_ORDRS_RS_MASK) 330 /*! @} */ 331 332 /*! @name ORDRZA - ORD0 Region Zone Assignment..ORD63 Region Zone Assignment */ 333 /*! @{ */ 334 335 #define OMU_ORDRZA_RZA_MASK (0xFU) 336 #define OMU_ORDRZA_RZA_SHIFT (0U) 337 #define OMU_ORDRZA_RZA_WIDTH (4U) 338 #define OMU_ORDRZA_RZA(x) (((uint32_t)(((uint32_t)(x)) << OMU_ORDRZA_RZA_SHIFT)) & OMU_ORDRZA_RZA_MASK) 339 /*! @} */ 340 341 /*! 342 * @} 343 */ /* end of group OMU_Register_Masks */ 344 345 /*! 346 * @} 347 */ /* end of group OMU_Peripheral_Access_Layer */ 348 349 #endif /* #if !defined(S32Z2_OMU_H_) */ 350
