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Searched refs:NUMBER_OF_CORES (Results 1 – 25 of 38) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k3/Rte/src/
DSchM_Adc.c102 …CACHE(msr_ADC_EXCLUSIVE_AREA_00) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …ADC_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_ADC_EXCLUSIVE_AREA_01) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …ADC_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_ADC_EXCLUSIVE_AREA_02) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …ADC_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_ADC_EXCLUSIVE_AREA_03) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …ADC_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_ADC_EXCLUSIVE_AREA_04) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …ADC_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Mcl.c102 …CACHE(msr_MCL_EXCLUSIVE_AREA_00) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …MCL_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_MCL_EXCLUSIVE_AREA_01) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …MCL_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_MCL_EXCLUSIVE_AREA_02) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …MCL_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_MCL_EXCLUSIVE_AREA_03) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …MCL_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_MCL_EXCLUSIVE_AREA_04) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …MCL_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Icu.c102 …U_EXCLUSIVE_AREA_00) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …U_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …U_EXCLUSIVE_AREA_01) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …U_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …U_EXCLUSIVE_AREA_02) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …U_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …U_EXCLUSIVE_AREA_03) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …U_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …U_EXCLUSIVE_AREA_04) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …U_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Pwm.c102 …CACHE(msr_PWM_EXCLUSIVE_AREA_00) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …PWM_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_PWM_EXCLUSIVE_AREA_01) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …PWM_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_PWM_EXCLUSIVE_AREA_02) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …PWM_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_PWM_EXCLUSIVE_AREA_03) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …PWM_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_PWM_EXCLUSIVE_AREA_04) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …PWM_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Fls.c102 …CACHE(msr_FLS_EXCLUSIVE_AREA_10) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
103 …FLS_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
104 …CACHE(msr_FLS_EXCLUSIVE_AREA_11) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
105 …FLS_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
106 …CACHE(msr_FLS_EXCLUSIVE_AREA_12) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
107 …FLS_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
108 …CACHE(msr_FLS_EXCLUSIVE_AREA_13) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
109 …FLS_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
110 …CACHE(msr_FLS_EXCLUSIVE_AREA_14) static volatile uint32 msr_FLS_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
111 …FLS_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_FLS_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
DSchM_Mcu.c102 …CACHE(msr_MCU_EXCLUSIVE_AREA_00) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …MCU_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_MCU_EXCLUSIVE_AREA_01) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …MCU_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_MCU_EXCLUSIVE_AREA_02) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …MCU_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
/hal_nxp-latest/s32/drivers/s32ze/Rte/src/
DSchM_Adc.c102 …CACHE(msr_ADC_EXCLUSIVE_AREA_00) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …ADC_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_ADC_EXCLUSIVE_AREA_01) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …ADC_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_ADC_EXCLUSIVE_AREA_02) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …ADC_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_ADC_EXCLUSIVE_AREA_03) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …ADC_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_ADC_EXCLUSIVE_AREA_04) static volatile uint32 msr_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …ADC_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_EthSwt_43_NETC.c102 …msr_ETHSWT_EXCLUSIVE_AREA_00) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …msr_ETHSWT_EXCLUSIVE_AREA_01) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …msr_ETHSWT_EXCLUSIVE_AREA_02) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …msr_ETHSWT_EXCLUSIVE_AREA_03) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …msr_ETHSWT_EXCLUSIVE_AREA_04) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Pwm.c102 …CACHE(msr_PWM_EXCLUSIVE_AREA_00) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …PWM_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_PWM_EXCLUSIVE_AREA_01) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …PWM_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_PWM_EXCLUSIVE_AREA_03) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
107 …PWM_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
108 …CACHE(msr_PWM_EXCLUSIVE_AREA_04) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
109 …PWM_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
110 …CACHE(msr_PWM_EXCLUSIVE_AREA_05) static volatile uint32 msr_PWM_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
111 …PWM_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_PWM_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
[all …]
DSchM_Mcl.c102 …CACHE(msr_MCL_EXCLUSIVE_AREA_00) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …MCL_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_MCL_EXCLUSIVE_AREA_01) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …MCL_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_MCL_EXCLUSIVE_AREA_02) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …MCL_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_MCL_EXCLUSIVE_AREA_03) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …MCL_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_MCL_EXCLUSIVE_AREA_04) static volatile uint32 msr_MCL_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …MCL_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_MCL_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Icu.c102 …CACHE(msr_ICU_EXCLUSIVE_AREA_00) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …ICU_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_ICU_EXCLUSIVE_AREA_01) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …ICU_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_ICU_EXCLUSIVE_AREA_02) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …ICU_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_ICU_EXCLUSIVE_AREA_03) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …ICU_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_ICU_EXCLUSIVE_AREA_04) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …ICU_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Eth_43_NETC.c102 …CACHE(msr_ETH_EXCLUSIVE_AREA_00) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …ETH_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_ETH_EXCLUSIVE_AREA_01) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …ETH_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_ETH_EXCLUSIVE_AREA_02) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …ETH_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_ETH_EXCLUSIVE_AREA_03) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …ETH_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_ETH_EXCLUSIVE_AREA_04) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …ETH_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Uart.c102 …CHE(msr_UART_EXCLUSIVE_AREA_00) static volatile uint32 msr_UART_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …RT_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CHE(msr_UART_EXCLUSIVE_AREA_01) static volatile uint32 msr_UART_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …RT_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CHE(msr_UART_EXCLUSIVE_AREA_02) static volatile uint32 msr_UART_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …RT_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CHE(msr_UART_EXCLUSIVE_AREA_03) static volatile uint32 msr_UART_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …RT_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CHE(msr_UART_EXCLUSIVE_AREA_04) static volatile uint32 msr_UART_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …RT_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_UART_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Can_43_CANEXCEL.c102 …CACHE(msr_CAN_EXCLUSIVE_AREA_00) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …CAN_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_CAN_EXCLUSIVE_AREA_01) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …CAN_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_CAN_EXCLUSIVE_AREA_02) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …CAN_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_CAN_EXCLUSIVE_AREA_03) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …CAN_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_CAN_EXCLUSIVE_AREA_04) static volatile uint32 msr_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …CAN_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_CAN_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Spi.c102 …CACHE(msr_SPI_EXCLUSIVE_AREA_00) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …SPI_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_SPI_EXCLUSIVE_AREA_01) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …SPI_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_SPI_EXCLUSIVE_AREA_02) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …SPI_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …CACHE(msr_SPI_EXCLUSIVE_AREA_03) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …SPI_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …CACHE(msr_SPI_EXCLUSIVE_AREA_04) static volatile uint32 msr_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …SPI_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Platform.c102 …PLATFORM_EXCLUSIVE_AREA_00) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …XCLUSIVE_AREA_00) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …PLATFORM_EXCLUSIVE_AREA_01) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …XCLUSIVE_AREA_01) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …PLATFORM_EXCLUSIVE_AREA_02) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …XCLUSIVE_AREA_02) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 …PLATFORM_EXCLUSIVE_AREA_03) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 …XCLUSIVE_AREA_03) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 …PLATFORM_EXCLUSIVE_AREA_04) static volatile uint32 msr_PLATFORM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 …XCLUSIVE_AREA_04) static volatile uint32 reentry_guard_PLATFORM_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
[all …]
DSchM_Mem_43_EXFLS.c102 …CACHE(msr_MEM_EXCLUSIVE_AREA_10) static volatile uint32 msr_MEM_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
103 …MEM_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_MEM_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
104 …CACHE(msr_MEM_EXCLUSIVE_AREA_11) static volatile uint32 msr_MEM_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
105 …MEM_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_MEM_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
106 …CACHE(msr_MEM_EXCLUSIVE_AREA_12) static volatile uint32 msr_MEM_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
107 …MEM_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_MEM_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
108 …CACHE(msr_MEM_EXCLUSIVE_AREA_13) static volatile uint32 msr_MEM_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
109 …MEM_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_MEM_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
110 …CACHE(msr_MEM_EXCLUSIVE_AREA_14) static volatile uint32 msr_MEM_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
111 …MEM_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_MEM_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
DSchM_Mcu.c102 …CACHE(msr_MCU_EXCLUSIVE_AREA_00) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …MCU_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_MCU_EXCLUSIVE_AREA_01) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …MCU_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_MCU_EXCLUSIVE_AREA_02) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …MCU_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
/hal_nxp-latest/s32/drivers/s32k1/Rte/src/
DSchM_Mcu.c102 …CACHE(msr_MCU_EXCLUSIVE_AREA_00) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 …MCU_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 …CACHE(msr_MCU_EXCLUSIVE_AREA_01) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 …MCU_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 …CACHE(msr_MCU_EXCLUSIVE_AREA_02) static volatile uint32 msr_MCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 …MCU_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_MCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
/hal_nxp-latest/s32/drivers/s32k3/Rte/include/
DSchM_Mcu.h54 #define NUMBER_OF_CORES (uint8)(4U) macro
DSchM_Fls.h54 #define NUMBER_OF_CORES (uint8)(4U) macro
/hal_nxp-latest/s32/drivers/s32ze/Rte/include/
DSchM_Mcu.h54 #define NUMBER_OF_CORES (uint8)(14U) macro
DSchM_Mem_43_EXFLS.h54 #define NUMBER_OF_CORES (uint8)(14U) macro
DSchM_Platform.h54 #define NUMBER_OF_CORES (uint8)(14U) macro
/hal_nxp-latest/s32/drivers/s32k1/Rte/include/
DSchM_Mcu.h54 #define NUMBER_OF_CORES (uint8)(1U) macro

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