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Searched refs:NPU_INTR_EVENT_MODE_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h47419 #define NPU_INTR_EVENT_MODE_MASK (0xC0U) macro
47422 … (((uint32_t)(((uint32_t)(x)) << NPU_INTR_EVENT_MODE_SHIFT)) & NPU_INTR_EVENT_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h50181 #define NPU_INTR_EVENT_MODE_MASK (0xC0U) macro
50184 … (((uint32_t)(((uint32_t)(x)) << NPU_INTR_EVENT_MODE_SHIFT)) & NPU_INTR_EVENT_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h50157 #define NPU_INTR_EVENT_MODE_MASK (0xC0U) macro
50160 … (((uint32_t)(((uint32_t)(x)) << NPU_INTR_EVENT_MODE_SHIFT)) & NPU_INTR_EVENT_MODE_MASK)