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Searched refs:NPU_FORMAT_INTRLVRES_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h47091 #define NPU_FORMAT_INTRLVRES_MASK (0x200U) macro
47094 … (((uint32_t)(((uint32_t)(x)) << NPU_FORMAT_INTRLVRES_SHIFT)) & NPU_FORMAT_INTRLVRES_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h49853 #define NPU_FORMAT_INTRLVRES_MASK (0x200U) macro
49856 … (((uint32_t)(((uint32_t)(x)) << NPU_FORMAT_INTRLVRES_SHIFT)) & NPU_FORMAT_INTRLVRES_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h49829 #define NPU_FORMAT_INTRLVRES_MASK (0x200U) macro
49832 … (((uint32_t)(((uint32_t)(x)) << NPU_FORMAT_INTRLVRES_SHIFT)) & NPU_FORMAT_INTRLVRES_MASK)