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Searched refs:NPU_FLUSH_BATCH_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h47380 #define NPU_FLUSH_BATCH_MASK (0x2U) macro
47383 … (((uint32_t)(((uint32_t)(x)) << NPU_FLUSH_BATCH_SHIFT)) & NPU_FLUSH_BATCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h50142 #define NPU_FLUSH_BATCH_MASK (0x2U) macro
50145 … (((uint32_t)(((uint32_t)(x)) << NPU_FLUSH_BATCH_SHIFT)) & NPU_FLUSH_BATCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h50118 #define NPU_FLUSH_BATCH_MASK (0x2U) macro
50121 … (((uint32_t)(((uint32_t)(x)) << NPU_FLUSH_BATCH_SHIFT)) & NPU_FLUSH_BATCH_MASK)