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Searched refs:NPU_CANVAS_LOAD_OUTER_BATCH_INC_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h47633 #define NPU_CANVAS_LOAD_OUTER_BATCH_INC_MASK (0xFFFFF000U) macro
47636 …(((uint32_t)(x)) << NPU_CANVAS_LOAD_OUTER_BATCH_INC_SHIFT)) & NPU_CANVAS_LOAD_OUTER_BATCH_INC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h50395 #define NPU_CANVAS_LOAD_OUTER_BATCH_INC_MASK (0xFFFFF000U) macro
50398 …(((uint32_t)(x)) << NPU_CANVAS_LOAD_OUTER_BATCH_INC_SHIFT)) & NPU_CANVAS_LOAD_OUTER_BATCH_INC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h50371 #define NPU_CANVAS_LOAD_OUTER_BATCH_INC_MASK (0xFFFFF000U) macro
50374 …(((uint32_t)(x)) << NPU_CANVAS_LOAD_OUTER_BATCH_INC_SHIFT)) & NPU_CANVAS_LOAD_OUTER_BATCH_INC_MASK)