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Searched refs:NPU_CANVAS_LOAD_BATCH_COUNT_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h47614 #define NPU_CANVAS_LOAD_BATCH_COUNT_MASK (0xFFFU) macro
47617 …int32_t)(((uint32_t)(x)) << NPU_CANVAS_LOAD_BATCH_COUNT_SHIFT)) & NPU_CANVAS_LOAD_BATCH_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_ezhv.h50376 #define NPU_CANVAS_LOAD_BATCH_COUNT_MASK (0xFFFU) macro
50379 …int32_t)(((uint32_t)(x)) << NPU_CANVAS_LOAD_BATCH_COUNT_SHIFT)) & NPU_CANVAS_LOAD_BATCH_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_ezhv.h50352 #define NPU_CANVAS_LOAD_BATCH_COUNT_MASK (0xFFFU) macro
50355 …int32_t)(((uint32_t)(x)) << NPU_CANVAS_LOAD_BATCH_COUNT_SHIFT)) & NPU_CANVAS_LOAD_BATCH_COUNT_MASK)