Searched refs:NIC_ENET1G_RX_BASE (Results 1 – 7 of 7) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/ |
| D | fsl_nic301.h | 50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) macro
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/ |
| D | fsl_nic301.h | 50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) macro
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/ |
| D | fsl_nic301.h | 50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) macro
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/ |
| D | fsl_nic301.h | 50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) macro
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/ |
| D | fsl_nic301.h | 50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) macro
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/ |
| D | fsl_nic301.h | 50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) macro
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/ |
| D | fsl_nic301.h | 50 #define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) macro
77 kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET,
95 kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET,
113 kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET,
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