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Searched refs:NIC_DCP_BASE (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_nic301.h43 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
82 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
92 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_nic301.h43 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
82 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
92 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_nic301.h43 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
82 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
92 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_nic301.h43 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
62 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
82 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
92 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_nic301.h48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
110 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_nic301.h48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
110 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_nic301.h48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
110 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_nic301.h48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
110 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_nic301.h48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
99 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
110 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_nic301.h48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
70 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
83 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
96 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_nic301.h48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000) macro
70 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
83 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
96 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,