1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F3_SI1.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_NETC_F3_SI1 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F3_SI1_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F3_SI1_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F3_SI1 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F3_SI1_Peripheral_Access_Layer NETC_F3_SI1 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F3_SI1 - Size of Registers Arrays */ 72 #define NETC_F3_SI1_SI_BOOT_LOAD_COUNT 2u 73 #define NETC_F3_SI1_TX_MSI_COUNT 18u 74 #define NETC_F3_SI1_RX_GRP_COUNT 18u 75 #define NETC_F3_SI1_BDR_NUM_COUNT 18u 76 77 /** NETC_F3_SI1 - Register Layout Typedef */ 78 typedef struct { 79 __IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0 */ 80 __I uint32_t SISR; /**< Station interface status register, offset: 0x4 */ 81 uint8_t RESERVED_0[16]; 82 __I uint32_t SICTR0; /**< Station interface current time register 0, offset: 0x18 */ 83 __I uint32_t SICTR1; /**< Station interface current time register 1, offset: 0x1C */ 84 __I uint32_t SIPCAPR0; /**< Station interface port capability register 0, offset: 0x20 */ 85 __I uint32_t SIPCAPR1; /**< Station interface port capability register 1, offset: 0x24 */ 86 uint8_t RESERVED_1[16]; 87 __IO uint32_t SIRBGCR; /**< Station interface receive BDR group control register, offset: 0x38 */ 88 uint8_t RESERVED_2[4]; 89 __IO uint32_t SIBCAR; /**< Station interface buffer cache attribute register, offset: 0x40 */ 90 uint8_t RESERVED_3[4]; 91 __IO uint32_t SICCAR; /**< Station interface command cache attribute register, offset: 0x48 */ 92 uint8_t RESERVED_4[52]; 93 __I uint32_t SIPMAR0; /**< Station interface primary MAC address register 0, offset: 0x80 */ 94 __I uint32_t SIPMAR1; /**< Station interface primary MAC address register 1, offset: 0x84 */ 95 uint8_t RESERVED_5[8]; 96 __I uint32_t SICVLANR1; /**< Station interface custom VLAN register 1, offset: 0x90 */ 97 __I uint32_t SICVLANR2; /**< Station interface custom VLAN register 2, offset: 0x94 */ 98 uint8_t RESERVED_6[104]; 99 __IO uint32_t SIVLANIPVMR0; /**< Station interface VLAN to IPV mapping register 0, offset: 0x100 */ 100 __IO uint32_t SIVLANIPVMR1; /**< Station interface VLAN to IPV mapping register 1, offset: 0x104 */ 101 uint8_t RESERVED_7[72]; 102 __IO uint32_t SIIPVBDRMR0; /**< Station interface IPV to ring mapping register, offset: 0x150 */ 103 uint8_t RESERVED_8[176]; 104 union { /* offset: 0x204 */ 105 struct NETC_F3_SI1_MSGSR_VSI_A { /* offset: 0x204 */ 106 __I uint32_t VSIMSGSR; /**< Virtual station interface message send register, offset: 0x204 */ 107 __I uint32_t VSIMSGRR; /**< Virtual station interface message receive register, offset: 0x208 */ 108 uint8_t RESERVED_0[4]; 109 __IO uint32_t VSIMSGSNDAR0; /**< Virtual station interface message send register 0, offset: 0x210 */ 110 __IO uint32_t VSIMSGSNDAR1; /**< Virtual station interface message send address register 1, offset: 0x214 */ 111 } VSI_A; 112 } MSGSR; 113 uint8_t RESERVED_9[232]; 114 __I uint32_t SIROCT0; /**< Station interface receive octets counter (ifInOctets) 0, offset: 0x300 */ 115 __I uint32_t SIROCT1; /**< Station interface receive octets counter (ifInOctets) 1, offset: 0x304 */ 116 __I uint32_t SIRFRM0; /**< Station interface receive frame counter (aFrameReceivedOK) 0, offset: 0x308 */ 117 __I uint32_t SIRFRM1; /**< Station interface receive frame counter (aFrameReceivedOK) 1, offset: 0x30C */ 118 __I uint32_t SIRUCA0; /**< Station interface receive unicast frame counter (ifInUcastPkts) 0, offset: 0x310 */ 119 __I uint32_t SIRUCA1; /**< Station interface receive unicast frame counter (ifInUcastPkts) 1, offset: 0x314 */ 120 __I uint32_t SIRMCA0; /**< Station interface receive multicast frame counter (ifInMulticastPkts) 0, offset: 0x318 */ 121 __I uint32_t SIRMCA1; /**< Station interface receive multicast frame counter (ifInMulticastPkts) 1, offset: 0x31C */ 122 __I uint32_t SITOCT0; /**< Station interface transmit octets counter (ifOutOctets) 0, offset: 0x320 */ 123 __I uint32_t SITOCT1; /**< Station interface transmit octets counter (ifOutOctets) 1, offset: 0x324 */ 124 __I uint32_t SITFRM0; /**< Station interface transmit frame counter (aFrameTransmittedOK) 0, offset: 0x328 */ 125 __I uint32_t SITFRM1; /**< Station interface transmit frame counter (aFrameTransmittedOK) 1, offset: 0x32C */ 126 __I uint32_t SITUCA0; /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 0, offset: 0x330 */ 127 __I uint32_t SITUCA1; /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 1, offset: 0x334 */ 128 __I uint32_t SITMCA0; /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 0, offset: 0x338 */ 129 __I uint32_t SITMCA1; /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 1, offset: 0x33C */ 130 uint8_t RESERVED_10[176]; 131 __I uint32_t SIBLPR[NETC_F3_SI1_SI_BOOT_LOAD_COUNT]; /**< Station interface boot loader parameter register 0..Station interface boot loader parameter register 1, array offset: 0x3F0, array step: 0x4 */ 132 uint8_t RESERVED_11[1032]; 133 __IO uint32_t SICBDRMR; /**< Station interface command BDR mode register, offset: 0x800 */ 134 __I uint32_t SICBDRSR; /**< Station interface command BDR status register, offset: 0x804 */ 135 uint8_t RESERVED_12[8]; 136 __IO uint32_t SICBDRBAR0; /**< Station interface command BDR base address register 0, offset: 0x810 */ 137 __IO uint32_t SICBDRBAR1; /**< Station interface command BDR base address register 1, offset: 0x814 */ 138 __IO uint32_t SICBDRPIR; /**< Station interface command BDR producer index register, offset: 0x818 */ 139 __IO uint32_t SICBDRCIR; /**< Station interface command BDR consumer index register, offset: 0x81C */ 140 __IO uint32_t SICBDRLENR; /**< Station interface command BDR length register, offset: 0x820 */ 141 uint8_t RESERVED_13[124]; 142 __IO uint32_t SICBDRIER; /**< Station interface command BDR interrupt enable register, offset: 0x8A0 */ 143 __IO uint32_t SICBDRIDR; /**< Station interface command BDR interrupt detect register, offset: 0x8A4 */ 144 uint8_t RESERVED_14[88]; 145 __I uint32_t SICAPR0; /**< Station interface capability register 0, offset: 0x900 */ 146 __I uint32_t SICAPR1; /**< Station interface capability register 1, offset: 0x904 */ 147 __I uint32_t SICAPR2; /**< Station interface capability register 2, offset: 0x908 */ 148 uint8_t RESERVED_15[244]; 149 union { /* offset: 0xA00 */ 150 struct NETC_F3_SI1_INTERRUPT_VSI { /* offset: 0xA00 */ 151 __IO uint32_t VSIIER; /**< Virtual station interface interrupt enable register, offset: 0xA00 */ 152 uint8_t RESERVED_0[4]; 153 __IO uint32_t VSIIDR; /**< Virtual station interface interrupt detect register, offset: 0xA08 */ 154 } VSI; 155 } INTERRUPT; 156 uint8_t RESERVED_16[12]; 157 __IO uint32_t SITXIDR0; /**< Station interface transmit interrupt detect register 0, offset: 0xA18 */ 158 __IO uint32_t SITXIDR1; /**< Station interface transmit interrupt detect register 1, offset: 0xA1C */ 159 uint8_t RESERVED_17[8]; 160 __IO uint32_t SIRXIDR0; /**< Station interface receive interrupt detect register 0, offset: 0xA28 */ 161 __IO uint32_t SIRXIDR1; /**< Station interface receive interrupt detect register 1, offset: 0xA2C */ 162 __IO uint32_t SIMSIVR; /**< Station interface MSI-X vector register, offset: 0xA30 */ 163 __IO uint32_t SICMSIVR; /**< Station interface command MSI-X vector register, offset: 0xA34 */ 164 uint8_t RESERVED_18[8]; 165 __IO uint32_t SITMRIER; /**< Station interface timer interrupt enable register, offset: 0xA40 */ 166 __IO uint32_t SITMRIDR; /**< Station interface timer interrupt detect register, offset: 0xA44 */ 167 uint8_t RESERVED_19[4]; 168 __IO uint32_t SITMRMSIVR; /**< Station interface timer MSI-X vector register, offset: 0xA4C */ 169 uint8_t RESERVED_20[176]; 170 __IO uint32_t SIMSITRVR[NETC_F3_SI1_TX_MSI_COUNT]; /**< Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 17 vector register, array offset: 0xB00, array step: 0x4 */ 171 uint8_t RESERVED_21[56]; 172 __IO uint32_t SIMSIRRVR[NETC_F3_SI1_RX_GRP_COUNT]; /**< Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 17 vector register, array offset: 0xB80, array step: 0x4 */ 173 uint8_t RESERVED_22[568]; 174 __IO uint32_t SICMECR; /**< Station interface correctable memory error configuration register, offset: 0xE00 */ 175 __IO uint32_t SICMESR; /**< Station interface correctable memory error status register, offset: 0xE04 */ 176 uint8_t RESERVED_23[4]; 177 __I uint32_t SICMECTR; /**< Station interface correctable memory error count register, offset: 0xE0C */ 178 __IO uint32_t SIUPECR; /**< Station interface uncorrectable programming error configuration register, offset: 0xE10 */ 179 __IO uint32_t SIUPESR; /**< Station interface uncorrectable programming error status register, offset: 0xE14 */ 180 uint8_t RESERVED_24[4]; 181 __I uint32_t SIUPECTR; /**< Station interface uncorrectable programming error count register, offset: 0xE1C */ 182 __IO uint32_t SIUNSBECR; /**< Station interface uncorrectable non-fatal system bus error configuration register, offset: 0xE20 */ 183 __IO uint32_t SIUNSBESR; /**< Station interface uncorrectable non-fatal system bus error status register, offset: 0xE24 */ 184 uint8_t RESERVED_25[4]; 185 __I uint32_t SIUNSBECTR; /**< Station interface uncorrectable non-fatal system bus error count register, offset: 0xE2C */ 186 __IO uint32_t SIUFSBECR; /**< Station interface uncorrectable fatal system bus error configuration register, offset: 0xE30 */ 187 __IO uint32_t SIUFSBESR; /**< Station interface uncorrectable fatal system bus error status register, offset: 0xE34 */ 188 uint8_t RESERVED_26[8]; 189 __IO uint32_t SIUNMECR; /**< Station interface uncorrectable non-fatal memory error configuration register, offset: 0xE40 */ 190 __IO uint32_t SIUNMESR0; /**< Station interface uncorrectable non-fatal memory error status register 0, offset: 0xE44 */ 191 __I uint32_t SIUNMESR1; /**< Station interface uncorrectable non-fatal memory error status register 1, offset: 0xE48 */ 192 __I uint32_t SIUNMECTR; /**< Station interface uncorrectable non-fatal memory error count register, offset: 0xE4C */ 193 __IO uint32_t SIUFMECR; /**< Station interface uncorrectable fatal memory error configuration register, offset: 0xE50 */ 194 __IO uint32_t SIUFMESR0; /**< Station interface uncorrectable fatal memory error status register 0, offset: 0xE54 */ 195 __I uint32_t SIUFMESR1; /**< Station interface uncorrectable fatal memory error status register 1, offset: 0xE58 */ 196 uint8_t RESERVED_27[4]; 197 __IO uint32_t SIUNIECR; /**< Station interface uncorrectable non-fatal integrity error configuration register, offset: 0xE60 */ 198 __IO uint32_t SIUNIESR; /**< Station interface uncorrectable non-fatal integrity error status register, offset: 0xE64 */ 199 uint8_t RESERVED_28[4]; 200 __I uint32_t SIUNIECTR; /**< Station interface uncorrectable non-fatal integrity error count register, offset: 0xE6C */ 201 __IO uint32_t SIUFIECR; /**< Station interface uncorrectable fatal integrity error configuration register, offset: 0xE70 */ 202 __IO uint32_t SIUFIESR; /**< Station interface uncorrectable fatal integrity error status register, offset: 0xE74 */ 203 uint8_t RESERVED_29[392]; 204 __I uint32_t SIMAFTCAPR; /**< Station interface MAC address filter table capability register, offset: 0x1000 */ 205 uint8_t RESERVED_30[252]; 206 __I uint32_t SIVFTCAPR; /**< Station interface VLAN filter table capability register, offset: 0x1100 */ 207 uint8_t RESERVED_31[252]; 208 __I uint32_t SIRFSCAPR; /**< Station interface RFS capability register, offset: 0x1200 */ 209 uint8_t RESERVED_32[28156]; 210 struct NETC_F3_SI1_BDR_NUM { /* offset: 0x8000, array step: 0x200 */ 211 __IO uint32_t TBMR; /**< Tx BDR 0 mode register..Tx BDR 17 mode register, array offset: 0x8000, array step: 0x200 */ 212 __IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status register, array offset: 0x8004, array step: 0x200 */ 213 uint8_t RESERVED_0[8]; 214 __IO uint32_t TBBAR0; /**< Tx BDR 0 base address register 0..Tx BDR 17 base address register 0, array offset: 0x8010, array step: 0x200 */ 215 __IO uint32_t TBBAR1; /**< Tx BDR 0 base address register 1..Tx BDR 17 base address register 1, array offset: 0x8014, array step: 0x200 */ 216 __IO uint32_t TBPIR; /**< Tx BDR 0 producer index register..Tx BDR 17 producer index register, array offset: 0x8018, array step: 0x200 */ 217 __IO uint32_t TBCIR; /**< Tx BDR 0 consumer index register..Tx BDR 17 consumer index register, array offset: 0x801C, array step: 0x200 */ 218 __IO uint32_t TBLENR; /**< Tx BDR 0 length register..Tx BDR 17 length register, array offset: 0x8020, array step: 0x200 */ 219 uint8_t RESERVED_1[124]; 220 __IO uint32_t TBIER; /**< Tx BDR 0 interrupt enable register..Tx BDR 17 interrupt enable register, array offset: 0x80A0, array step: 0x200 */ 221 __I uint32_t TBIDR; /**< Tx BDR 0 interrupt detect register..Tx BDR 17 interrupt detect register, array offset: 0x80A4, array step: 0x200 */ 222 __IO uint32_t TBICR0; /**< Tx BDR 0 interrupt coalescing register 0..Tx BDR 17 interrupt coalescing register 0, array offset: 0x80A8, array step: 0x200 */ 223 __IO uint32_t TBICR1; /**< Tx BDR 0 interrupt coalescing register 1..Tx BDR 17 interrupt coalescing register 1, array offset: 0x80AC, array step: 0x200 */ 224 uint8_t RESERVED_2[80]; 225 __IO uint32_t RBMR; /**< Rx BDR 0 mode register..Rx BDR 17 mode register, array offset: 0x8100, array step: 0x200 */ 226 __IO uint32_t RBSR; /**< Rx BDR 0 status register..Rx BDR 17 status register, array offset: 0x8104, array step: 0x200 */ 227 __IO uint32_t RBBSR; /**< Rx BDR 0 buffer size register..Rx BDR 17 buffer size register, array offset: 0x8108, array step: 0x200 */ 228 __IO uint32_t RBCIR; /**< Rx BDR 0 consumer index register..Rx BDR 17 consumer index register, array offset: 0x810C, array step: 0x200 */ 229 __IO uint32_t RBBAR0; /**< Rx BDR 0 base address register 0..Rx BDR 17 base address register 0, array offset: 0x8110, array step: 0x200 */ 230 __IO uint32_t RBBAR1; /**< Rx BDR 0 base address register 1..Rx BDR 17 base address register 1, array offset: 0x8114, array step: 0x200 */ 231 __IO uint32_t RBPIR; /**< Rx BDR 0 producer index register..Rx BDR 17 producer index register, array offset: 0x8118, array step: 0x200 */ 232 uint8_t RESERVED_3[4]; 233 __IO uint32_t RBLENR; /**< Rx BDR 0 length register..Rx BDR 17 length register, array offset: 0x8120, array step: 0x200 */ 234 uint8_t RESERVED_4[92]; 235 __I uint32_t RBDCR; /**< Rx BDR 0 drop count register..Rx BDR 17 drop count register, array offset: 0x8180, array step: 0x200 */ 236 uint8_t RESERVED_5[28]; 237 __IO uint32_t RBIER; /**< Rx BDR 0 interrupt enable register..Rx BDR 17 interrupt enable register, array offset: 0x81A0, array step: 0x200 */ 238 __I uint32_t RBIDR; /**< Rx BDR 0 interrupt detect register..Rx BDR 17 interrupt detect register, array offset: 0x81A4, array step: 0x200 */ 239 __IO uint32_t RBICR0; /**< Rx BDR 0 interrupt coalescing register 0..Rx BDR 17 interrupt coalescing register 0, array offset: 0x81A8, array step: 0x200 */ 240 __IO uint32_t RBICR1; /**< Rx BDR 0 interrupt coalescing register 1..Rx BDR 17 interrupt coalescing register 1, array offset: 0x81AC, array step: 0x200 */ 241 uint8_t RESERVED_6[80]; 242 } BDR_NUM[NETC_F3_SI1_BDR_NUM_COUNT]; 243 } NETC_F3_SI1_Type, *NETC_F3_SI1_MemMapPtr; 244 245 /** Number of instances of the NETC_F3_SI1 module. */ 246 #define NETC_F3_SI1_INSTANCE_COUNT (1u) 247 248 /* NETC_F3_SI1 - Peripheral instance base addresses */ 249 /** Peripheral NETC__ENETC0_SI1 base address */ 250 #define IP_NETC__ENETC0_SI1_BASE (0x74BC0000u) 251 /** Peripheral NETC__ENETC0_SI1 base pointer */ 252 #define IP_NETC__ENETC0_SI1 ((NETC_F3_SI1_Type *)IP_NETC__ENETC0_SI1_BASE) 253 /** Array initializer of NETC_F3_SI1 peripheral base addresses */ 254 #define IP_NETC_F3_SI1_BASE_ADDRS { IP_NETC__ENETC0_SI1_BASE } 255 /** Array initializer of NETC_F3_SI1 peripheral base pointers */ 256 #define IP_NETC_F3_SI1_BASE_PTRS { IP_NETC__ENETC0_SI1 } 257 258 /* ---------------------------------------------------------------------------- 259 -- NETC_F3_SI1 Register Masks 260 ---------------------------------------------------------------------------- */ 261 262 /*! 263 * @addtogroup NETC_F3_SI1_Register_Masks NETC_F3_SI1 Register Masks 264 * @{ 265 */ 266 267 /*! @name SIMR - Station interface mode register */ 268 /*! @{ */ 269 270 #define NETC_F3_SI1_SIMR_RSSE_MASK (0x1U) 271 #define NETC_F3_SI1_SIMR_RSSE_SHIFT (0U) 272 #define NETC_F3_SI1_SIMR_RSSE_WIDTH (1U) 273 #define NETC_F3_SI1_SIMR_RSSE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMR_RSSE_SHIFT)) & NETC_F3_SI1_SIMR_RSSE_MASK) 274 275 #define NETC_F3_SI1_SIMR_RNUM_MASK (0x2U) 276 #define NETC_F3_SI1_SIMR_RNUM_SHIFT (1U) 277 #define NETC_F3_SI1_SIMR_RNUM_WIDTH (1U) 278 #define NETC_F3_SI1_SIMR_RNUM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMR_RNUM_SHIFT)) & NETC_F3_SI1_SIMR_RNUM_MASK) 279 280 #define NETC_F3_SI1_SIMR_RNMM_MASK (0x4U) 281 #define NETC_F3_SI1_SIMR_RNMM_SHIFT (2U) 282 #define NETC_F3_SI1_SIMR_RNMM_WIDTH (1U) 283 #define NETC_F3_SI1_SIMR_RNMM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMR_RNMM_SHIFT)) & NETC_F3_SI1_SIMR_RNMM_MASK) 284 285 #define NETC_F3_SI1_SIMR_RNBM_MASK (0x8U) 286 #define NETC_F3_SI1_SIMR_RNBM_SHIFT (3U) 287 #define NETC_F3_SI1_SIMR_RNBM_WIDTH (1U) 288 #define NETC_F3_SI1_SIMR_RNBM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMR_RNBM_SHIFT)) & NETC_F3_SI1_SIMR_RNBM_MASK) 289 290 #define NETC_F3_SI1_SIMR_V2IPVE_MASK (0x10U) 291 #define NETC_F3_SI1_SIMR_V2IPVE_SHIFT (4U) 292 #define NETC_F3_SI1_SIMR_V2IPVE_WIDTH (1U) 293 #define NETC_F3_SI1_SIMR_V2IPVE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMR_V2IPVE_SHIFT)) & NETC_F3_SI1_SIMR_V2IPVE_MASK) 294 295 #define NETC_F3_SI1_SIMR_DEFAULT_RX_GROUP_MASK (0x10000U) 296 #define NETC_F3_SI1_SIMR_DEFAULT_RX_GROUP_SHIFT (16U) 297 #define NETC_F3_SI1_SIMR_DEFAULT_RX_GROUP_WIDTH (1U) 298 #define NETC_F3_SI1_SIMR_DEFAULT_RX_GROUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMR_DEFAULT_RX_GROUP_SHIFT)) & NETC_F3_SI1_SIMR_DEFAULT_RX_GROUP_MASK) 299 300 #define NETC_F3_SI1_SIMR_EN_MASK (0x80000000U) 301 #define NETC_F3_SI1_SIMR_EN_SHIFT (31U) 302 #define NETC_F3_SI1_SIMR_EN_WIDTH (1U) 303 #define NETC_F3_SI1_SIMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMR_EN_SHIFT)) & NETC_F3_SI1_SIMR_EN_MASK) 304 /*! @} */ 305 306 /*! @name SISR - Station interface status register */ 307 /*! @{ */ 308 309 #define NETC_F3_SI1_SISR_TX_BUSY_MASK (0x1U) 310 #define NETC_F3_SI1_SISR_TX_BUSY_SHIFT (0U) 311 #define NETC_F3_SI1_SISR_TX_BUSY_WIDTH (1U) 312 #define NETC_F3_SI1_SISR_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SISR_TX_BUSY_SHIFT)) & NETC_F3_SI1_SISR_TX_BUSY_MASK) 313 314 #define NETC_F3_SI1_SISR_MAC_UP_MASK (0x2U) 315 #define NETC_F3_SI1_SISR_MAC_UP_SHIFT (1U) 316 #define NETC_F3_SI1_SISR_MAC_UP_WIDTH (1U) 317 #define NETC_F3_SI1_SISR_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SISR_MAC_UP_SHIFT)) & NETC_F3_SI1_SISR_MAC_UP_MASK) 318 319 #define NETC_F3_SI1_SISR_MAC_MP_MASK (0x4U) 320 #define NETC_F3_SI1_SISR_MAC_MP_SHIFT (2U) 321 #define NETC_F3_SI1_SISR_MAC_MP_WIDTH (1U) 322 #define NETC_F3_SI1_SISR_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SISR_MAC_MP_SHIFT)) & NETC_F3_SI1_SISR_MAC_MP_MASK) 323 324 #define NETC_F3_SI1_SISR_VLAN_P_MASK (0x8U) 325 #define NETC_F3_SI1_SISR_VLAN_P_SHIFT (3U) 326 #define NETC_F3_SI1_SISR_VLAN_P_WIDTH (1U) 327 #define NETC_F3_SI1_SISR_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SISR_VLAN_P_SHIFT)) & NETC_F3_SI1_SISR_VLAN_P_MASK) 328 329 #define NETC_F3_SI1_SISR_VLAN_UTA_MASK (0x10U) 330 #define NETC_F3_SI1_SISR_VLAN_UTA_SHIFT (4U) 331 #define NETC_F3_SI1_SISR_VLAN_UTA_WIDTH (1U) 332 #define NETC_F3_SI1_SISR_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SISR_VLAN_UTA_SHIFT)) & NETC_F3_SI1_SISR_VLAN_UTA_MASK) 333 /*! @} */ 334 335 /*! @name SICTR0 - Station interface current time register 0 */ 336 /*! @{ */ 337 338 #define NETC_F3_SI1_SICTR0_CURR_TIME_MASK (0xFFFFFFFFU) 339 #define NETC_F3_SI1_SICTR0_CURR_TIME_SHIFT (0U) 340 #define NETC_F3_SI1_SICTR0_CURR_TIME_WIDTH (32U) 341 #define NETC_F3_SI1_SICTR0_CURR_TIME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICTR0_CURR_TIME_SHIFT)) & NETC_F3_SI1_SICTR0_CURR_TIME_MASK) 342 /*! @} */ 343 344 /*! @name SICTR1 - Station interface current time register 1 */ 345 /*! @{ */ 346 347 #define NETC_F3_SI1_SICTR1_CURR_TIME_MASK (0xFFFFFFFFU) 348 #define NETC_F3_SI1_SICTR1_CURR_TIME_SHIFT (0U) 349 #define NETC_F3_SI1_SICTR1_CURR_TIME_WIDTH (32U) 350 #define NETC_F3_SI1_SICTR1_CURR_TIME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICTR1_CURR_TIME_SHIFT)) & NETC_F3_SI1_SICTR1_CURR_TIME_MASK) 351 /*! @} */ 352 353 /*! @name SIPCAPR0 - Station interface port capability register 0 */ 354 /*! @{ */ 355 356 #define NETC_F3_SI1_SIPCAPR0_RFS_MASK (0x4U) 357 #define NETC_F3_SI1_SIPCAPR0_RFS_SHIFT (2U) 358 #define NETC_F3_SI1_SIPCAPR0_RFS_WIDTH (1U) 359 #define NETC_F3_SI1_SIPCAPR0_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_RFS_SHIFT)) & NETC_F3_SI1_SIPCAPR0_RFS_MASK) 360 361 #define NETC_F3_SI1_SIPCAPR0_FP_MASK (0x8U) 362 #define NETC_F3_SI1_SIPCAPR0_FP_SHIFT (3U) 363 #define NETC_F3_SI1_SIPCAPR0_FP_WIDTH (1U) 364 #define NETC_F3_SI1_SIPCAPR0_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_FP_SHIFT)) & NETC_F3_SI1_SIPCAPR0_FP_MASK) 365 366 #define NETC_F3_SI1_SIPCAPR0_TGS_MASK (0x10U) 367 #define NETC_F3_SI1_SIPCAPR0_TGS_SHIFT (4U) 368 #define NETC_F3_SI1_SIPCAPR0_TGS_WIDTH (1U) 369 #define NETC_F3_SI1_SIPCAPR0_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_TGS_SHIFT)) & NETC_F3_SI1_SIPCAPR0_TGS_MASK) 370 371 #define NETC_F3_SI1_SIPCAPR0_TSD_MASK (0x20U) 372 #define NETC_F3_SI1_SIPCAPR0_TSD_SHIFT (5U) 373 #define NETC_F3_SI1_SIPCAPR0_TSD_WIDTH (1U) 374 #define NETC_F3_SI1_SIPCAPR0_TSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_TSD_SHIFT)) & NETC_F3_SI1_SIPCAPR0_TSD_MASK) 375 376 #define NETC_F3_SI1_SIPCAPR0_CBS_MASK (0x40U) 377 #define NETC_F3_SI1_SIPCAPR0_CBS_SHIFT (6U) 378 #define NETC_F3_SI1_SIPCAPR0_CBS_WIDTH (1U) 379 #define NETC_F3_SI1_SIPCAPR0_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_CBS_SHIFT)) & NETC_F3_SI1_SIPCAPR0_CBS_MASK) 380 381 #define NETC_F3_SI1_SIPCAPR0_RSS_MASK (0x100U) 382 #define NETC_F3_SI1_SIPCAPR0_RSS_SHIFT (8U) 383 #define NETC_F3_SI1_SIPCAPR0_RSS_WIDTH (1U) 384 #define NETC_F3_SI1_SIPCAPR0_RSS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_RSS_SHIFT)) & NETC_F3_SI1_SIPCAPR0_RSS_MASK) 385 386 #define NETC_F3_SI1_SIPCAPR0_PSFP_MASK (0x200U) 387 #define NETC_F3_SI1_SIPCAPR0_PSFP_SHIFT (9U) 388 #define NETC_F3_SI1_SIPCAPR0_PSFP_WIDTH (1U) 389 #define NETC_F3_SI1_SIPCAPR0_PSFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_PSFP_SHIFT)) & NETC_F3_SI1_SIPCAPR0_PSFP_MASK) 390 391 #define NETC_F3_SI1_SIPCAPR0_IPFLT_MASK (0x400U) 392 #define NETC_F3_SI1_SIPCAPR0_IPFLT_SHIFT (10U) 393 #define NETC_F3_SI1_SIPCAPR0_IPFLT_WIDTH (1U) 394 #define NETC_F3_SI1_SIPCAPR0_IPFLT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_IPFLT_SHIFT)) & NETC_F3_SI1_SIPCAPR0_IPFLT_MASK) 395 396 #define NETC_F3_SI1_SIPCAPR0_RP_MASK (0x800U) 397 #define NETC_F3_SI1_SIPCAPR0_RP_SHIFT (11U) 398 #define NETC_F3_SI1_SIPCAPR0_RP_WIDTH (1U) 399 #define NETC_F3_SI1_SIPCAPR0_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_RP_SHIFT)) & NETC_F3_SI1_SIPCAPR0_RP_MASK) 400 401 #define NETC_F3_SI1_SIPCAPR0_WO_MASK (0x2000U) 402 #define NETC_F3_SI1_SIPCAPR0_WO_SHIFT (13U) 403 #define NETC_F3_SI1_SIPCAPR0_WO_WIDTH (1U) 404 #define NETC_F3_SI1_SIPCAPR0_WO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_WO_SHIFT)) & NETC_F3_SI1_SIPCAPR0_WO_MASK) 405 406 #define NETC_F3_SI1_SIPCAPR0_FS_MASK (0x10000U) 407 #define NETC_F3_SI1_SIPCAPR0_FS_SHIFT (16U) 408 #define NETC_F3_SI1_SIPCAPR0_FS_WIDTH (1U) 409 #define NETC_F3_SI1_SIPCAPR0_FS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR0_FS_SHIFT)) & NETC_F3_SI1_SIPCAPR0_FS_MASK) 410 /*! @} */ 411 412 /*! @name SIPCAPR1 - Station interface port capability register 1 */ 413 /*! @{ */ 414 415 #define NETC_F3_SI1_SIPCAPR1_NUM_TCS_MASK (0x70U) 416 #define NETC_F3_SI1_SIPCAPR1_NUM_TCS_SHIFT (4U) 417 #define NETC_F3_SI1_SIPCAPR1_NUM_TCS_WIDTH (3U) 418 #define NETC_F3_SI1_SIPCAPR1_NUM_TCS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR1_NUM_TCS_SHIFT)) & NETC_F3_SI1_SIPCAPR1_NUM_TCS_MASK) 419 420 #define NETC_F3_SI1_SIPCAPR1_NUM_MCH_MASK (0x300U) 421 #define NETC_F3_SI1_SIPCAPR1_NUM_MCH_SHIFT (8U) 422 #define NETC_F3_SI1_SIPCAPR1_NUM_MCH_WIDTH (2U) 423 #define NETC_F3_SI1_SIPCAPR1_NUM_MCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR1_NUM_MCH_SHIFT)) & NETC_F3_SI1_SIPCAPR1_NUM_MCH_MASK) 424 425 #define NETC_F3_SI1_SIPCAPR1_NUM_UCH_MASK (0xC00U) 426 #define NETC_F3_SI1_SIPCAPR1_NUM_UCH_SHIFT (10U) 427 #define NETC_F3_SI1_SIPCAPR1_NUM_UCH_WIDTH (2U) 428 #define NETC_F3_SI1_SIPCAPR1_NUM_UCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR1_NUM_UCH_SHIFT)) & NETC_F3_SI1_SIPCAPR1_NUM_UCH_MASK) 429 430 #define NETC_F3_SI1_SIPCAPR1_NUM_MSIX_MASK (0x3F000U) 431 #define NETC_F3_SI1_SIPCAPR1_NUM_MSIX_SHIFT (12U) 432 #define NETC_F3_SI1_SIPCAPR1_NUM_MSIX_WIDTH (6U) 433 #define NETC_F3_SI1_SIPCAPR1_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR1_NUM_MSIX_SHIFT)) & NETC_F3_SI1_SIPCAPR1_NUM_MSIX_MASK) 434 435 #define NETC_F3_SI1_SIPCAPR1_NUM_IPV_MASK (0x80000000U) 436 #define NETC_F3_SI1_SIPCAPR1_NUM_IPV_SHIFT (31U) 437 #define NETC_F3_SI1_SIPCAPR1_NUM_IPV_WIDTH (1U) 438 #define NETC_F3_SI1_SIPCAPR1_NUM_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPCAPR1_NUM_IPV_SHIFT)) & NETC_F3_SI1_SIPCAPR1_NUM_IPV_MASK) 439 /*! @} */ 440 441 /*! @name SIRBGCR - Station interface receive BDR group control register */ 442 /*! @{ */ 443 444 #define NETC_F3_SI1_SIRBGCR_NUM_GROUPS_MASK (0x3U) 445 #define NETC_F3_SI1_SIRBGCR_NUM_GROUPS_SHIFT (0U) 446 #define NETC_F3_SI1_SIRBGCR_NUM_GROUPS_WIDTH (2U) 447 #define NETC_F3_SI1_SIRBGCR_NUM_GROUPS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRBGCR_NUM_GROUPS_SHIFT)) & NETC_F3_SI1_SIRBGCR_NUM_GROUPS_MASK) 448 449 #define NETC_F3_SI1_SIRBGCR_RINGS_PER_GROUP_MASK (0x70000U) 450 #define NETC_F3_SI1_SIRBGCR_RINGS_PER_GROUP_SHIFT (16U) 451 #define NETC_F3_SI1_SIRBGCR_RINGS_PER_GROUP_WIDTH (3U) 452 #define NETC_F3_SI1_SIRBGCR_RINGS_PER_GROUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRBGCR_RINGS_PER_GROUP_SHIFT)) & NETC_F3_SI1_SIRBGCR_RINGS_PER_GROUP_MASK) 453 /*! @} */ 454 455 /*! @name SIBCAR - Station interface buffer cache attribute register */ 456 /*! @{ */ 457 458 #define NETC_F3_SI1_SIBCAR_BD_WRCACHE_MASK (0xFU) 459 #define NETC_F3_SI1_SIBCAR_BD_WRCACHE_SHIFT (0U) 460 #define NETC_F3_SI1_SIBCAR_BD_WRCACHE_WIDTH (4U) 461 #define NETC_F3_SI1_SIBCAR_BD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_BD_WRCACHE_SHIFT)) & NETC_F3_SI1_SIBCAR_BD_WRCACHE_MASK) 462 463 #define NETC_F3_SI1_SIBCAR_BD_WRDOMAIN_MASK (0x30U) 464 #define NETC_F3_SI1_SIBCAR_BD_WRDOMAIN_SHIFT (4U) 465 #define NETC_F3_SI1_SIBCAR_BD_WRDOMAIN_WIDTH (2U) 466 #define NETC_F3_SI1_SIBCAR_BD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_BD_WRDOMAIN_SHIFT)) & NETC_F3_SI1_SIBCAR_BD_WRDOMAIN_MASK) 467 468 #define NETC_F3_SI1_SIBCAR_BD_WRSNP_MASK (0x40U) 469 #define NETC_F3_SI1_SIBCAR_BD_WRSNP_SHIFT (6U) 470 #define NETC_F3_SI1_SIBCAR_BD_WRSNP_WIDTH (1U) 471 #define NETC_F3_SI1_SIBCAR_BD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_BD_WRSNP_SHIFT)) & NETC_F3_SI1_SIBCAR_BD_WRSNP_MASK) 472 473 #define NETC_F3_SI1_SIBCAR_WRCACHE_MASK (0xF00U) 474 #define NETC_F3_SI1_SIBCAR_WRCACHE_SHIFT (8U) 475 #define NETC_F3_SI1_SIBCAR_WRCACHE_WIDTH (4U) 476 #define NETC_F3_SI1_SIBCAR_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_WRCACHE_SHIFT)) & NETC_F3_SI1_SIBCAR_WRCACHE_MASK) 477 478 #define NETC_F3_SI1_SIBCAR_WRDOMAIN_MASK (0x3000U) 479 #define NETC_F3_SI1_SIBCAR_WRDOMAIN_SHIFT (12U) 480 #define NETC_F3_SI1_SIBCAR_WRDOMAIN_WIDTH (2U) 481 #define NETC_F3_SI1_SIBCAR_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_WRDOMAIN_SHIFT)) & NETC_F3_SI1_SIBCAR_WRDOMAIN_MASK) 482 483 #define NETC_F3_SI1_SIBCAR_WRSNP_MASK (0x4000U) 484 #define NETC_F3_SI1_SIBCAR_WRSNP_SHIFT (14U) 485 #define NETC_F3_SI1_SIBCAR_WRSNP_WIDTH (1U) 486 #define NETC_F3_SI1_SIBCAR_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_WRSNP_SHIFT)) & NETC_F3_SI1_SIBCAR_WRSNP_MASK) 487 488 #define NETC_F3_SI1_SIBCAR_BD_RDCACHE_MASK (0xF0000U) 489 #define NETC_F3_SI1_SIBCAR_BD_RDCACHE_SHIFT (16U) 490 #define NETC_F3_SI1_SIBCAR_BD_RDCACHE_WIDTH (4U) 491 #define NETC_F3_SI1_SIBCAR_BD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_BD_RDCACHE_SHIFT)) & NETC_F3_SI1_SIBCAR_BD_RDCACHE_MASK) 492 493 #define NETC_F3_SI1_SIBCAR_BD_RDDOMAIN_MASK (0x300000U) 494 #define NETC_F3_SI1_SIBCAR_BD_RDDOMAIN_SHIFT (20U) 495 #define NETC_F3_SI1_SIBCAR_BD_RDDOMAIN_WIDTH (2U) 496 #define NETC_F3_SI1_SIBCAR_BD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_BD_RDDOMAIN_SHIFT)) & NETC_F3_SI1_SIBCAR_BD_RDDOMAIN_MASK) 497 498 #define NETC_F3_SI1_SIBCAR_BD_RDSNP_MASK (0x400000U) 499 #define NETC_F3_SI1_SIBCAR_BD_RDSNP_SHIFT (22U) 500 #define NETC_F3_SI1_SIBCAR_BD_RDSNP_WIDTH (1U) 501 #define NETC_F3_SI1_SIBCAR_BD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_BD_RDSNP_SHIFT)) & NETC_F3_SI1_SIBCAR_BD_RDSNP_MASK) 502 503 #define NETC_F3_SI1_SIBCAR_RDCACHE_MASK (0xF000000U) 504 #define NETC_F3_SI1_SIBCAR_RDCACHE_SHIFT (24U) 505 #define NETC_F3_SI1_SIBCAR_RDCACHE_WIDTH (4U) 506 #define NETC_F3_SI1_SIBCAR_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_RDCACHE_SHIFT)) & NETC_F3_SI1_SIBCAR_RDCACHE_MASK) 507 508 #define NETC_F3_SI1_SIBCAR_RDDOMAIN_MASK (0x30000000U) 509 #define NETC_F3_SI1_SIBCAR_RDDOMAIN_SHIFT (28U) 510 #define NETC_F3_SI1_SIBCAR_RDDOMAIN_WIDTH (2U) 511 #define NETC_F3_SI1_SIBCAR_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_RDDOMAIN_SHIFT)) & NETC_F3_SI1_SIBCAR_RDDOMAIN_MASK) 512 513 #define NETC_F3_SI1_SIBCAR_RDSNP_MASK (0x40000000U) 514 #define NETC_F3_SI1_SIBCAR_RDSNP_SHIFT (30U) 515 #define NETC_F3_SI1_SIBCAR_RDSNP_WIDTH (1U) 516 #define NETC_F3_SI1_SIBCAR_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBCAR_RDSNP_SHIFT)) & NETC_F3_SI1_SIBCAR_RDSNP_MASK) 517 /*! @} */ 518 519 /*! @name SICCAR - Station interface command cache attribute register */ 520 /*! @{ */ 521 522 #define NETC_F3_SI1_SICCAR_CBD_WRCACHE_MASK (0xFU) 523 #define NETC_F3_SI1_SICCAR_CBD_WRCACHE_SHIFT (0U) 524 #define NETC_F3_SI1_SICCAR_CBD_WRCACHE_WIDTH (4U) 525 #define NETC_F3_SI1_SICCAR_CBD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CBD_WRCACHE_SHIFT)) & NETC_F3_SI1_SICCAR_CBD_WRCACHE_MASK) 526 527 #define NETC_F3_SI1_SICCAR_CBD_WRDOMAIN_MASK (0x30U) 528 #define NETC_F3_SI1_SICCAR_CBD_WRDOMAIN_SHIFT (4U) 529 #define NETC_F3_SI1_SICCAR_CBD_WRDOMAIN_WIDTH (2U) 530 #define NETC_F3_SI1_SICCAR_CBD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CBD_WRDOMAIN_SHIFT)) & NETC_F3_SI1_SICCAR_CBD_WRDOMAIN_MASK) 531 532 #define NETC_F3_SI1_SICCAR_CBD_WRSNP_MASK (0x40U) 533 #define NETC_F3_SI1_SICCAR_CBD_WRSNP_SHIFT (6U) 534 #define NETC_F3_SI1_SICCAR_CBD_WRSNP_WIDTH (1U) 535 #define NETC_F3_SI1_SICCAR_CBD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CBD_WRSNP_SHIFT)) & NETC_F3_SI1_SICCAR_CBD_WRSNP_MASK) 536 537 #define NETC_F3_SI1_SICCAR_CWRCACHE_MASK (0xF00U) 538 #define NETC_F3_SI1_SICCAR_CWRCACHE_SHIFT (8U) 539 #define NETC_F3_SI1_SICCAR_CWRCACHE_WIDTH (4U) 540 #define NETC_F3_SI1_SICCAR_CWRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CWRCACHE_SHIFT)) & NETC_F3_SI1_SICCAR_CWRCACHE_MASK) 541 542 #define NETC_F3_SI1_SICCAR_CWRDOMAIN_MASK (0x3000U) 543 #define NETC_F3_SI1_SICCAR_CWRDOMAIN_SHIFT (12U) 544 #define NETC_F3_SI1_SICCAR_CWRDOMAIN_WIDTH (2U) 545 #define NETC_F3_SI1_SICCAR_CWRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CWRDOMAIN_SHIFT)) & NETC_F3_SI1_SICCAR_CWRDOMAIN_MASK) 546 547 #define NETC_F3_SI1_SICCAR_CWRSNP_MASK (0x4000U) 548 #define NETC_F3_SI1_SICCAR_CWRSNP_SHIFT (14U) 549 #define NETC_F3_SI1_SICCAR_CWRSNP_WIDTH (1U) 550 #define NETC_F3_SI1_SICCAR_CWRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CWRSNP_SHIFT)) & NETC_F3_SI1_SICCAR_CWRSNP_MASK) 551 552 #define NETC_F3_SI1_SICCAR_CBD_RDCACHE_MASK (0xF0000U) 553 #define NETC_F3_SI1_SICCAR_CBD_RDCACHE_SHIFT (16U) 554 #define NETC_F3_SI1_SICCAR_CBD_RDCACHE_WIDTH (4U) 555 #define NETC_F3_SI1_SICCAR_CBD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CBD_RDCACHE_SHIFT)) & NETC_F3_SI1_SICCAR_CBD_RDCACHE_MASK) 556 557 #define NETC_F3_SI1_SICCAR_CBD_RDDOMAIN_MASK (0x300000U) 558 #define NETC_F3_SI1_SICCAR_CBD_RDDOMAIN_SHIFT (20U) 559 #define NETC_F3_SI1_SICCAR_CBD_RDDOMAIN_WIDTH (2U) 560 #define NETC_F3_SI1_SICCAR_CBD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CBD_RDDOMAIN_SHIFT)) & NETC_F3_SI1_SICCAR_CBD_RDDOMAIN_MASK) 561 562 #define NETC_F3_SI1_SICCAR_CBD_RDSNP_MASK (0x400000U) 563 #define NETC_F3_SI1_SICCAR_CBD_RDSNP_SHIFT (22U) 564 #define NETC_F3_SI1_SICCAR_CBD_RDSNP_WIDTH (1U) 565 #define NETC_F3_SI1_SICCAR_CBD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CBD_RDSNP_SHIFT)) & NETC_F3_SI1_SICCAR_CBD_RDSNP_MASK) 566 567 #define NETC_F3_SI1_SICCAR_CRDCACHE_MASK (0xF000000U) 568 #define NETC_F3_SI1_SICCAR_CRDCACHE_SHIFT (24U) 569 #define NETC_F3_SI1_SICCAR_CRDCACHE_WIDTH (4U) 570 #define NETC_F3_SI1_SICCAR_CRDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CRDCACHE_SHIFT)) & NETC_F3_SI1_SICCAR_CRDCACHE_MASK) 571 572 #define NETC_F3_SI1_SICCAR_CRDDOMAIN_MASK (0x30000000U) 573 #define NETC_F3_SI1_SICCAR_CRDDOMAIN_SHIFT (28U) 574 #define NETC_F3_SI1_SICCAR_CRDDOMAIN_WIDTH (2U) 575 #define NETC_F3_SI1_SICCAR_CRDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CRDDOMAIN_SHIFT)) & NETC_F3_SI1_SICCAR_CRDDOMAIN_MASK) 576 577 #define NETC_F3_SI1_SICCAR_CRDSNP_MASK (0x40000000U) 578 #define NETC_F3_SI1_SICCAR_CRDSNP_SHIFT (30U) 579 #define NETC_F3_SI1_SICCAR_CRDSNP_WIDTH (1U) 580 #define NETC_F3_SI1_SICCAR_CRDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICCAR_CRDSNP_SHIFT)) & NETC_F3_SI1_SICCAR_CRDSNP_MASK) 581 /*! @} */ 582 583 /*! @name SIPMAR0 - Station interface primary MAC address register 0 */ 584 /*! @{ */ 585 586 #define NETC_F3_SI1_SIPMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) 587 #define NETC_F3_SI1_SIPMAR0_PRIM_MAC_ADDR_SHIFT (0U) 588 #define NETC_F3_SI1_SIPMAR0_PRIM_MAC_ADDR_WIDTH (32U) 589 #define NETC_F3_SI1_SIPMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPMAR0_PRIM_MAC_ADDR_SHIFT)) & NETC_F3_SI1_SIPMAR0_PRIM_MAC_ADDR_MASK) 590 /*! @} */ 591 592 /*! @name SIPMAR1 - Station interface primary MAC address register 1 */ 593 /*! @{ */ 594 595 #define NETC_F3_SI1_SIPMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) 596 #define NETC_F3_SI1_SIPMAR1_PRIM_MAC_ADDR_SHIFT (0U) 597 #define NETC_F3_SI1_SIPMAR1_PRIM_MAC_ADDR_WIDTH (16U) 598 #define NETC_F3_SI1_SIPMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIPMAR1_PRIM_MAC_ADDR_SHIFT)) & NETC_F3_SI1_SIPMAR1_PRIM_MAC_ADDR_MASK) 599 /*! @} */ 600 601 /*! @name SICVLANR1 - Station interface custom VLAN register 1 */ 602 /*! @{ */ 603 604 #define NETC_F3_SI1_SICVLANR1_ETYPE_MASK (0xFFFFU) 605 #define NETC_F3_SI1_SICVLANR1_ETYPE_SHIFT (0U) 606 #define NETC_F3_SI1_SICVLANR1_ETYPE_WIDTH (16U) 607 #define NETC_F3_SI1_SICVLANR1_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICVLANR1_ETYPE_SHIFT)) & NETC_F3_SI1_SICVLANR1_ETYPE_MASK) 608 609 #define NETC_F3_SI1_SICVLANR1_V_MASK (0x80000000U) 610 #define NETC_F3_SI1_SICVLANR1_V_SHIFT (31U) 611 #define NETC_F3_SI1_SICVLANR1_V_WIDTH (1U) 612 #define NETC_F3_SI1_SICVLANR1_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICVLANR1_V_SHIFT)) & NETC_F3_SI1_SICVLANR1_V_MASK) 613 /*! @} */ 614 615 /*! @name SICVLANR2 - Station interface custom VLAN register 2 */ 616 /*! @{ */ 617 618 #define NETC_F3_SI1_SICVLANR2_ETYPE_MASK (0xFFFFU) 619 #define NETC_F3_SI1_SICVLANR2_ETYPE_SHIFT (0U) 620 #define NETC_F3_SI1_SICVLANR2_ETYPE_WIDTH (16U) 621 #define NETC_F3_SI1_SICVLANR2_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICVLANR2_ETYPE_SHIFT)) & NETC_F3_SI1_SICVLANR2_ETYPE_MASK) 622 623 #define NETC_F3_SI1_SICVLANR2_V_MASK (0x80000000U) 624 #define NETC_F3_SI1_SICVLANR2_V_SHIFT (31U) 625 #define NETC_F3_SI1_SICVLANR2_V_WIDTH (1U) 626 #define NETC_F3_SI1_SICVLANR2_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICVLANR2_V_SHIFT)) & NETC_F3_SI1_SICVLANR2_V_MASK) 627 /*! @} */ 628 629 /*! @name SIVLANIPVMR0 - Station interface VLAN to IPV mapping register 0 */ 630 /*! @{ */ 631 632 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_0_MASK (0xFU) 633 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_0_SHIFT (0U) 634 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_0_WIDTH (4U) 635 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_0_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_0_MASK) 636 637 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_1_MASK (0xF0U) 638 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_1_SHIFT (4U) 639 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_1_WIDTH (4U) 640 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_1_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_1_MASK) 641 642 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_2_MASK (0xF00U) 643 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_2_SHIFT (8U) 644 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_2_WIDTH (4U) 645 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_2_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_2_MASK) 646 647 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_3_MASK (0xF000U) 648 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_3_SHIFT (12U) 649 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_3_WIDTH (4U) 650 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_3_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_3_MASK) 651 652 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_4_MASK (0xF0000U) 653 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_4_SHIFT (16U) 654 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_4_WIDTH (4U) 655 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_4_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_4_MASK) 656 657 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_5_MASK (0xF00000U) 658 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_5_SHIFT (20U) 659 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_5_WIDTH (4U) 660 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_5_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_5_MASK) 661 662 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_6_MASK (0xF000000U) 663 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_6_SHIFT (24U) 664 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_6_WIDTH (4U) 665 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_6_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_6_MASK) 666 667 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_7_MASK (0xF0000000U) 668 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_7_SHIFT (28U) 669 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_7_WIDTH (4U) 670 #define NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_7_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR0_PCP_DEI_7_MASK) 671 /*! @} */ 672 673 /*! @name SIVLANIPVMR1 - Station interface VLAN to IPV mapping register 1 */ 674 /*! @{ */ 675 676 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_8_MASK (0xFU) 677 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_8_SHIFT (0U) 678 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_8_WIDTH (4U) 679 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_8_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_8_MASK) 680 681 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_9_MASK (0xF0U) 682 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_9_SHIFT (4U) 683 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_9_WIDTH (4U) 684 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_9_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_9_MASK) 685 686 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_10_MASK (0xF00U) 687 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_10_SHIFT (8U) 688 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_10_WIDTH (4U) 689 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_10_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_10_MASK) 690 691 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_11_MASK (0xF000U) 692 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_11_SHIFT (12U) 693 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_11_WIDTH (4U) 694 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_11_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_11_MASK) 695 696 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_12_MASK (0xF0000U) 697 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_12_SHIFT (16U) 698 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_12_WIDTH (4U) 699 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_12_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_12_MASK) 700 701 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_13_MASK (0xF00000U) 702 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_13_SHIFT (20U) 703 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_13_WIDTH (4U) 704 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_13_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_13_MASK) 705 706 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_14_MASK (0xF000000U) 707 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_14_SHIFT (24U) 708 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_14_WIDTH (4U) 709 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_14_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_14_MASK) 710 711 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_15_MASK (0xF0000000U) 712 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_15_SHIFT (28U) 713 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_15_WIDTH (4U) 714 #define NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_15_SHIFT)) & NETC_F3_SI1_SIVLANIPVMR1_PCP_DEI_15_MASK) 715 /*! @} */ 716 717 /*! @name SIIPVBDRMR0 - Station interface IPV to ring mapping register */ 718 /*! @{ */ 719 720 #define NETC_F3_SI1_SIIPVBDRMR0_IPV0BDR_MASK (0x7U) 721 #define NETC_F3_SI1_SIIPVBDRMR0_IPV0BDR_SHIFT (0U) 722 #define NETC_F3_SI1_SIIPVBDRMR0_IPV0BDR_WIDTH (3U) 723 #define NETC_F3_SI1_SIIPVBDRMR0_IPV0BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV0BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV0BDR_MASK) 724 725 #define NETC_F3_SI1_SIIPVBDRMR0_IPV1BDR_MASK (0x70U) 726 #define NETC_F3_SI1_SIIPVBDRMR0_IPV1BDR_SHIFT (4U) 727 #define NETC_F3_SI1_SIIPVBDRMR0_IPV1BDR_WIDTH (3U) 728 #define NETC_F3_SI1_SIIPVBDRMR0_IPV1BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV1BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV1BDR_MASK) 729 730 #define NETC_F3_SI1_SIIPVBDRMR0_IPV2BDR_MASK (0x700U) 731 #define NETC_F3_SI1_SIIPVBDRMR0_IPV2BDR_SHIFT (8U) 732 #define NETC_F3_SI1_SIIPVBDRMR0_IPV2BDR_WIDTH (3U) 733 #define NETC_F3_SI1_SIIPVBDRMR0_IPV2BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV2BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV2BDR_MASK) 734 735 #define NETC_F3_SI1_SIIPVBDRMR0_IPV3BDR_MASK (0x7000U) 736 #define NETC_F3_SI1_SIIPVBDRMR0_IPV3BDR_SHIFT (12U) 737 #define NETC_F3_SI1_SIIPVBDRMR0_IPV3BDR_WIDTH (3U) 738 #define NETC_F3_SI1_SIIPVBDRMR0_IPV3BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV3BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV3BDR_MASK) 739 740 #define NETC_F3_SI1_SIIPVBDRMR0_IPV4BDR_MASK (0x70000U) 741 #define NETC_F3_SI1_SIIPVBDRMR0_IPV4BDR_SHIFT (16U) 742 #define NETC_F3_SI1_SIIPVBDRMR0_IPV4BDR_WIDTH (3U) 743 #define NETC_F3_SI1_SIIPVBDRMR0_IPV4BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV4BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV4BDR_MASK) 744 745 #define NETC_F3_SI1_SIIPVBDRMR0_IPV5BDR_MASK (0x700000U) 746 #define NETC_F3_SI1_SIIPVBDRMR0_IPV5BDR_SHIFT (20U) 747 #define NETC_F3_SI1_SIIPVBDRMR0_IPV5BDR_WIDTH (3U) 748 #define NETC_F3_SI1_SIIPVBDRMR0_IPV5BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV5BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV5BDR_MASK) 749 750 #define NETC_F3_SI1_SIIPVBDRMR0_IPV6BDR_MASK (0x7000000U) 751 #define NETC_F3_SI1_SIIPVBDRMR0_IPV6BDR_SHIFT (24U) 752 #define NETC_F3_SI1_SIIPVBDRMR0_IPV6BDR_WIDTH (3U) 753 #define NETC_F3_SI1_SIIPVBDRMR0_IPV6BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV6BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV6BDR_MASK) 754 755 #define NETC_F3_SI1_SIIPVBDRMR0_IPV7BDR_MASK (0x70000000U) 756 #define NETC_F3_SI1_SIIPVBDRMR0_IPV7BDR_SHIFT (28U) 757 #define NETC_F3_SI1_SIIPVBDRMR0_IPV7BDR_WIDTH (3U) 758 #define NETC_F3_SI1_SIIPVBDRMR0_IPV7BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIIPVBDRMR0_IPV7BDR_SHIFT)) & NETC_F3_SI1_SIIPVBDRMR0_IPV7BDR_MASK) 759 /*! @} */ 760 761 /*! @name VSIMSGSR - Virtual station interface message send register */ 762 /*! @{ */ 763 764 #define NETC_F3_SI1_VSIMSGSR_MB_MASK (0x1U) 765 #define NETC_F3_SI1_VSIMSGSR_MB_SHIFT (0U) 766 #define NETC_F3_SI1_VSIMSGSR_MB_WIDTH (1U) 767 #define NETC_F3_SI1_VSIMSGSR_MB(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGSR_MB_SHIFT)) & NETC_F3_SI1_VSIMSGSR_MB_MASK) 768 769 #define NETC_F3_SI1_VSIMSGSR_MS_MASK (0x2U) 770 #define NETC_F3_SI1_VSIMSGSR_MS_SHIFT (1U) 771 #define NETC_F3_SI1_VSIMSGSR_MS_WIDTH (1U) 772 #define NETC_F3_SI1_VSIMSGSR_MS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGSR_MS_SHIFT)) & NETC_F3_SI1_VSIMSGSR_MS_MASK) 773 774 #define NETC_F3_SI1_VSIMSGSR_MC_MASK (0xFFFF0000U) 775 #define NETC_F3_SI1_VSIMSGSR_MC_SHIFT (16U) 776 #define NETC_F3_SI1_VSIMSGSR_MC_WIDTH (16U) 777 #define NETC_F3_SI1_VSIMSGSR_MC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGSR_MC_SHIFT)) & NETC_F3_SI1_VSIMSGSR_MC_MASK) 778 /*! @} */ 779 780 /*! @name VSIMSGRR - Virtual station interface message receive register */ 781 /*! @{ */ 782 783 #define NETC_F3_SI1_VSIMSGRR_MR_MASK (0x1U) 784 #define NETC_F3_SI1_VSIMSGRR_MR_SHIFT (0U) 785 #define NETC_F3_SI1_VSIMSGRR_MR_WIDTH (1U) 786 #define NETC_F3_SI1_VSIMSGRR_MR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGRR_MR_SHIFT)) & NETC_F3_SI1_VSIMSGRR_MR_MASK) 787 788 #define NETC_F3_SI1_VSIMSGRR_MC_MASK (0xFFFF0000U) 789 #define NETC_F3_SI1_VSIMSGRR_MC_SHIFT (16U) 790 #define NETC_F3_SI1_VSIMSGRR_MC_WIDTH (16U) 791 #define NETC_F3_SI1_VSIMSGRR_MC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGRR_MC_SHIFT)) & NETC_F3_SI1_VSIMSGRR_MC_MASK) 792 /*! @} */ 793 794 /*! @name VSIMSGSNDAR0 - Virtual station interface message send register 0 */ 795 /*! @{ */ 796 797 #define NETC_F3_SI1_VSIMSGSNDAR0_MSIZE_MASK (0x1FU) 798 #define NETC_F3_SI1_VSIMSGSNDAR0_MSIZE_SHIFT (0U) 799 #define NETC_F3_SI1_VSIMSGSNDAR0_MSIZE_WIDTH (5U) 800 #define NETC_F3_SI1_VSIMSGSNDAR0_MSIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGSNDAR0_MSIZE_SHIFT)) & NETC_F3_SI1_VSIMSGSNDAR0_MSIZE_MASK) 801 802 #define NETC_F3_SI1_VSIMSGSNDAR0_ADDRL_MASK (0xFFFFFFC0U) 803 #define NETC_F3_SI1_VSIMSGSNDAR0_ADDRL_SHIFT (6U) 804 #define NETC_F3_SI1_VSIMSGSNDAR0_ADDRL_WIDTH (26U) 805 #define NETC_F3_SI1_VSIMSGSNDAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGSNDAR0_ADDRL_SHIFT)) & NETC_F3_SI1_VSIMSGSNDAR0_ADDRL_MASK) 806 /*! @} */ 807 808 /*! @name VSIMSGSNDAR1 - Virtual station interface message send address register 1 */ 809 /*! @{ */ 810 811 #define NETC_F3_SI1_VSIMSGSNDAR1_ADDRH_MASK (0xFFFFFFFFU) 812 #define NETC_F3_SI1_VSIMSGSNDAR1_ADDRH_SHIFT (0U) 813 #define NETC_F3_SI1_VSIMSGSNDAR1_ADDRH_WIDTH (32U) 814 #define NETC_F3_SI1_VSIMSGSNDAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIMSGSNDAR1_ADDRH_SHIFT)) & NETC_F3_SI1_VSIMSGSNDAR1_ADDRH_MASK) 815 /*! @} */ 816 817 /*! @name SIROCT0 - Station interface receive octets counter (ifInOctets) 0 */ 818 /*! @{ */ 819 820 #define NETC_F3_SI1_SIROCT0_ROCT_LOW_MASK (0xFFFFFFFFU) 821 #define NETC_F3_SI1_SIROCT0_ROCT_LOW_SHIFT (0U) 822 #define NETC_F3_SI1_SIROCT0_ROCT_LOW_WIDTH (32U) 823 #define NETC_F3_SI1_SIROCT0_ROCT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIROCT0_ROCT_LOW_SHIFT)) & NETC_F3_SI1_SIROCT0_ROCT_LOW_MASK) 824 /*! @} */ 825 826 /*! @name SIROCT1 - Station interface receive octets counter (ifInOctets) 1 */ 827 /*! @{ */ 828 829 #define NETC_F3_SI1_SIROCT1_ROCT_HIGH_MASK (0xFFFFFFFFU) 830 #define NETC_F3_SI1_SIROCT1_ROCT_HIGH_SHIFT (0U) 831 #define NETC_F3_SI1_SIROCT1_ROCT_HIGH_WIDTH (32U) 832 #define NETC_F3_SI1_SIROCT1_ROCT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIROCT1_ROCT_HIGH_SHIFT)) & NETC_F3_SI1_SIROCT1_ROCT_HIGH_MASK) 833 /*! @} */ 834 835 /*! @name SIRFRM0 - Station interface receive frame counter (aFrameReceivedOK) 0 */ 836 /*! @{ */ 837 838 #define NETC_F3_SI1_SIRFRM0_RFRM_LOW_MASK (0xFFFFFFFFU) 839 #define NETC_F3_SI1_SIRFRM0_RFRM_LOW_SHIFT (0U) 840 #define NETC_F3_SI1_SIRFRM0_RFRM_LOW_WIDTH (32U) 841 #define NETC_F3_SI1_SIRFRM0_RFRM_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRFRM0_RFRM_LOW_SHIFT)) & NETC_F3_SI1_SIRFRM0_RFRM_LOW_MASK) 842 /*! @} */ 843 844 /*! @name SIRFRM1 - Station interface receive frame counter (aFrameReceivedOK) 1 */ 845 /*! @{ */ 846 847 #define NETC_F3_SI1_SIRFRM1_RFRM_HIGH_MASK (0xFFFFFFFFU) 848 #define NETC_F3_SI1_SIRFRM1_RFRM_HIGH_SHIFT (0U) 849 #define NETC_F3_SI1_SIRFRM1_RFRM_HIGH_WIDTH (32U) 850 #define NETC_F3_SI1_SIRFRM1_RFRM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRFRM1_RFRM_HIGH_SHIFT)) & NETC_F3_SI1_SIRFRM1_RFRM_HIGH_MASK) 851 /*! @} */ 852 853 /*! @name SIRUCA0 - Station interface receive unicast frame counter (ifInUcastPkts) 0 */ 854 /*! @{ */ 855 856 #define NETC_F3_SI1_SIRUCA0_RUCA_LOW_MASK (0xFFFFFFFFU) 857 #define NETC_F3_SI1_SIRUCA0_RUCA_LOW_SHIFT (0U) 858 #define NETC_F3_SI1_SIRUCA0_RUCA_LOW_WIDTH (32U) 859 #define NETC_F3_SI1_SIRUCA0_RUCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRUCA0_RUCA_LOW_SHIFT)) & NETC_F3_SI1_SIRUCA0_RUCA_LOW_MASK) 860 /*! @} */ 861 862 /*! @name SIRUCA1 - Station interface receive unicast frame counter (ifInUcastPkts) 1 */ 863 /*! @{ */ 864 865 #define NETC_F3_SI1_SIRUCA1_RUCA_HIGH_MASK (0xFFFFFFFFU) 866 #define NETC_F3_SI1_SIRUCA1_RUCA_HIGH_SHIFT (0U) 867 #define NETC_F3_SI1_SIRUCA1_RUCA_HIGH_WIDTH (32U) 868 #define NETC_F3_SI1_SIRUCA1_RUCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRUCA1_RUCA_HIGH_SHIFT)) & NETC_F3_SI1_SIRUCA1_RUCA_HIGH_MASK) 869 /*! @} */ 870 871 /*! @name SIRMCA0 - Station interface receive multicast frame counter (ifInMulticastPkts) 0 */ 872 /*! @{ */ 873 874 #define NETC_F3_SI1_SIRMCA0_RMCA_LOW_MASK (0xFFFFFFFFU) 875 #define NETC_F3_SI1_SIRMCA0_RMCA_LOW_SHIFT (0U) 876 #define NETC_F3_SI1_SIRMCA0_RMCA_LOW_WIDTH (32U) 877 #define NETC_F3_SI1_SIRMCA0_RMCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRMCA0_RMCA_LOW_SHIFT)) & NETC_F3_SI1_SIRMCA0_RMCA_LOW_MASK) 878 /*! @} */ 879 880 /*! @name SIRMCA1 - Station interface receive multicast frame counter (ifInMulticastPkts) 1 */ 881 /*! @{ */ 882 883 #define NETC_F3_SI1_SIRMCA1_RMCA_HIGH_MASK (0xFFFFFFFFU) 884 #define NETC_F3_SI1_SIRMCA1_RMCA_HIGH_SHIFT (0U) 885 #define NETC_F3_SI1_SIRMCA1_RMCA_HIGH_WIDTH (32U) 886 #define NETC_F3_SI1_SIRMCA1_RMCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRMCA1_RMCA_HIGH_SHIFT)) & NETC_F3_SI1_SIRMCA1_RMCA_HIGH_MASK) 887 /*! @} */ 888 889 /*! @name SITOCT0 - Station interface transmit octets counter (ifOutOctets) 0 */ 890 /*! @{ */ 891 892 #define NETC_F3_SI1_SITOCT0_TOCT_LOW_MASK (0xFFFFFFFFU) 893 #define NETC_F3_SI1_SITOCT0_TOCT_LOW_SHIFT (0U) 894 #define NETC_F3_SI1_SITOCT0_TOCT_LOW_WIDTH (32U) 895 #define NETC_F3_SI1_SITOCT0_TOCT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITOCT0_TOCT_LOW_SHIFT)) & NETC_F3_SI1_SITOCT0_TOCT_LOW_MASK) 896 /*! @} */ 897 898 /*! @name SITOCT1 - Station interface transmit octets counter (ifOutOctets) 1 */ 899 /*! @{ */ 900 901 #define NETC_F3_SI1_SITOCT1_TOCT_HIGH_MASK (0xFFFFFFFFU) 902 #define NETC_F3_SI1_SITOCT1_TOCT_HIGH_SHIFT (0U) 903 #define NETC_F3_SI1_SITOCT1_TOCT_HIGH_WIDTH (32U) 904 #define NETC_F3_SI1_SITOCT1_TOCT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITOCT1_TOCT_HIGH_SHIFT)) & NETC_F3_SI1_SITOCT1_TOCT_HIGH_MASK) 905 /*! @} */ 906 907 /*! @name SITFRM0 - Station interface transmit frame counter (aFrameTransmittedOK) 0 */ 908 /*! @{ */ 909 910 #define NETC_F3_SI1_SITFRM0_TFRM_LOW_MASK (0xFFFFFFFFU) 911 #define NETC_F3_SI1_SITFRM0_TFRM_LOW_SHIFT (0U) 912 #define NETC_F3_SI1_SITFRM0_TFRM_LOW_WIDTH (32U) 913 #define NETC_F3_SI1_SITFRM0_TFRM_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITFRM0_TFRM_LOW_SHIFT)) & NETC_F3_SI1_SITFRM0_TFRM_LOW_MASK) 914 /*! @} */ 915 916 /*! @name SITFRM1 - Station interface transmit frame counter (aFrameTransmittedOK) 1 */ 917 /*! @{ */ 918 919 #define NETC_F3_SI1_SITFRM1_TFRM_HIGH_MASK (0xFFFFFFFFU) 920 #define NETC_F3_SI1_SITFRM1_TFRM_HIGH_SHIFT (0U) 921 #define NETC_F3_SI1_SITFRM1_TFRM_HIGH_WIDTH (32U) 922 #define NETC_F3_SI1_SITFRM1_TFRM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITFRM1_TFRM_HIGH_SHIFT)) & NETC_F3_SI1_SITFRM1_TFRM_HIGH_MASK) 923 /*! @} */ 924 925 /*! @name SITUCA0 - Station interface transmit unicast frame counter (ifOutUcastPkts) 0 */ 926 /*! @{ */ 927 928 #define NETC_F3_SI1_SITUCA0_TUCA_LOW_MASK (0xFFFFFFFFU) 929 #define NETC_F3_SI1_SITUCA0_TUCA_LOW_SHIFT (0U) 930 #define NETC_F3_SI1_SITUCA0_TUCA_LOW_WIDTH (32U) 931 #define NETC_F3_SI1_SITUCA0_TUCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITUCA0_TUCA_LOW_SHIFT)) & NETC_F3_SI1_SITUCA0_TUCA_LOW_MASK) 932 /*! @} */ 933 934 /*! @name SITUCA1 - Station interface transmit unicast frame counter (ifOutUcastPkts) 1 */ 935 /*! @{ */ 936 937 #define NETC_F3_SI1_SITUCA1_TUCA_HIGH_MASK (0xFFFFFFFFU) 938 #define NETC_F3_SI1_SITUCA1_TUCA_HIGH_SHIFT (0U) 939 #define NETC_F3_SI1_SITUCA1_TUCA_HIGH_WIDTH (32U) 940 #define NETC_F3_SI1_SITUCA1_TUCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITUCA1_TUCA_HIGH_SHIFT)) & NETC_F3_SI1_SITUCA1_TUCA_HIGH_MASK) 941 /*! @} */ 942 943 /*! @name SITMCA0 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 0 */ 944 /*! @{ */ 945 946 #define NETC_F3_SI1_SITMCA0_TMCA_LOW_MASK (0xFFFFFFFFU) 947 #define NETC_F3_SI1_SITMCA0_TMCA_LOW_SHIFT (0U) 948 #define NETC_F3_SI1_SITMCA0_TMCA_LOW_WIDTH (32U) 949 #define NETC_F3_SI1_SITMCA0_TMCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITMCA0_TMCA_LOW_SHIFT)) & NETC_F3_SI1_SITMCA0_TMCA_LOW_MASK) 950 /*! @} */ 951 952 /*! @name SITMCA1 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 1 */ 953 /*! @{ */ 954 955 #define NETC_F3_SI1_SITMCA1_TMCA_HIGH_MASK (0xFFFFFFFFU) 956 #define NETC_F3_SI1_SITMCA1_TMCA_HIGH_SHIFT (0U) 957 #define NETC_F3_SI1_SITMCA1_TMCA_HIGH_WIDTH (32U) 958 #define NETC_F3_SI1_SITMCA1_TMCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITMCA1_TMCA_HIGH_SHIFT)) & NETC_F3_SI1_SITMCA1_TMCA_HIGH_MASK) 959 /*! @} */ 960 961 /*! @name SIBLPR - Station interface boot loader parameter register 0..Station interface boot loader parameter register 1 */ 962 /*! @{ */ 963 964 #define NETC_F3_SI1_SIBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 965 #define NETC_F3_SI1_SIBLPR_PARAM_VAL_SHIFT (0U) 966 #define NETC_F3_SI1_SIBLPR_PARAM_VAL_WIDTH (32U) 967 #define NETC_F3_SI1_SIBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIBLPR_PARAM_VAL_SHIFT)) & NETC_F3_SI1_SIBLPR_PARAM_VAL_MASK) 968 /*! @} */ 969 970 /*! @name SICBDRMR - Station interface command BDR mode register */ 971 /*! @{ */ 972 973 #define NETC_F3_SI1_SICBDRMR_EN_MASK (0x80000000U) 974 #define NETC_F3_SI1_SICBDRMR_EN_SHIFT (31U) 975 #define NETC_F3_SI1_SICBDRMR_EN_WIDTH (1U) 976 #define NETC_F3_SI1_SICBDRMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRMR_EN_SHIFT)) & NETC_F3_SI1_SICBDRMR_EN_MASK) 977 /*! @} */ 978 979 /*! @name SICBDRSR - Station interface command BDR status register */ 980 /*! @{ */ 981 982 #define NETC_F3_SI1_SICBDRSR_BUSY_MASK (0x1U) 983 #define NETC_F3_SI1_SICBDRSR_BUSY_SHIFT (0U) 984 #define NETC_F3_SI1_SICBDRSR_BUSY_WIDTH (1U) 985 #define NETC_F3_SI1_SICBDRSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRSR_BUSY_SHIFT)) & NETC_F3_SI1_SICBDRSR_BUSY_MASK) 986 /*! @} */ 987 988 /*! @name SICBDRBAR0 - Station interface command BDR base address register 0 */ 989 /*! @{ */ 990 991 #define NETC_F3_SI1_SICBDRBAR0_ADDRL_MASK (0xFFFFFF80U) 992 #define NETC_F3_SI1_SICBDRBAR0_ADDRL_SHIFT (7U) 993 #define NETC_F3_SI1_SICBDRBAR0_ADDRL_WIDTH (25U) 994 #define NETC_F3_SI1_SICBDRBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRBAR0_ADDRL_SHIFT)) & NETC_F3_SI1_SICBDRBAR0_ADDRL_MASK) 995 /*! @} */ 996 997 /*! @name SICBDRBAR1 - Station interface command BDR base address register 1 */ 998 /*! @{ */ 999 1000 #define NETC_F3_SI1_SICBDRBAR1_ADDRH_MASK (0xFFFFFFFFU) 1001 #define NETC_F3_SI1_SICBDRBAR1_ADDRH_SHIFT (0U) 1002 #define NETC_F3_SI1_SICBDRBAR1_ADDRH_WIDTH (32U) 1003 #define NETC_F3_SI1_SICBDRBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRBAR1_ADDRH_SHIFT)) & NETC_F3_SI1_SICBDRBAR1_ADDRH_MASK) 1004 /*! @} */ 1005 1006 /*! @name SICBDRPIR - Station interface command BDR producer index register */ 1007 /*! @{ */ 1008 1009 #define NETC_F3_SI1_SICBDRPIR_BDR_INDEX_MASK (0x3FFU) 1010 #define NETC_F3_SI1_SICBDRPIR_BDR_INDEX_SHIFT (0U) 1011 #define NETC_F3_SI1_SICBDRPIR_BDR_INDEX_WIDTH (10U) 1012 #define NETC_F3_SI1_SICBDRPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRPIR_BDR_INDEX_SHIFT)) & NETC_F3_SI1_SICBDRPIR_BDR_INDEX_MASK) 1013 /*! @} */ 1014 1015 /*! @name SICBDRCIR - Station interface command BDR consumer index register */ 1016 /*! @{ */ 1017 1018 #define NETC_F3_SI1_SICBDRCIR_BDR_INDEX_MASK (0x3FFU) 1019 #define NETC_F3_SI1_SICBDRCIR_BDR_INDEX_SHIFT (0U) 1020 #define NETC_F3_SI1_SICBDRCIR_BDR_INDEX_WIDTH (10U) 1021 #define NETC_F3_SI1_SICBDRCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRCIR_BDR_INDEX_SHIFT)) & NETC_F3_SI1_SICBDRCIR_BDR_INDEX_MASK) 1022 /*! @} */ 1023 1024 /*! @name SICBDRLENR - Station interface command BDR length register */ 1025 /*! @{ */ 1026 1027 #define NETC_F3_SI1_SICBDRLENR_LENGTH_MASK (0x7F8U) 1028 #define NETC_F3_SI1_SICBDRLENR_LENGTH_SHIFT (3U) 1029 #define NETC_F3_SI1_SICBDRLENR_LENGTH_WIDTH (8U) 1030 #define NETC_F3_SI1_SICBDRLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRLENR_LENGTH_SHIFT)) & NETC_F3_SI1_SICBDRLENR_LENGTH_MASK) 1031 /*! @} */ 1032 1033 /*! @name SICBDRIER - Station interface command BDR interrupt enable register */ 1034 /*! @{ */ 1035 1036 #define NETC_F3_SI1_SICBDRIER_CBDCIE_MASK (0x1U) 1037 #define NETC_F3_SI1_SICBDRIER_CBDCIE_SHIFT (0U) 1038 #define NETC_F3_SI1_SICBDRIER_CBDCIE_WIDTH (1U) 1039 #define NETC_F3_SI1_SICBDRIER_CBDCIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRIER_CBDCIE_SHIFT)) & NETC_F3_SI1_SICBDRIER_CBDCIE_MASK) 1040 /*! @} */ 1041 1042 /*! @name SICBDRIDR - Station interface command BDR interrupt detect register */ 1043 /*! @{ */ 1044 1045 #define NETC_F3_SI1_SICBDRIDR_CBDC_MASK (0x1U) 1046 #define NETC_F3_SI1_SICBDRIDR_CBDC_SHIFT (0U) 1047 #define NETC_F3_SI1_SICBDRIDR_CBDC_WIDTH (1U) 1048 #define NETC_F3_SI1_SICBDRIDR_CBDC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICBDRIDR_CBDC_SHIFT)) & NETC_F3_SI1_SICBDRIDR_CBDC_MASK) 1049 /*! @} */ 1050 1051 /*! @name SICAPR0 - Station interface capability register 0 */ 1052 /*! @{ */ 1053 1054 #define NETC_F3_SI1_SICAPR0_NUM_TX_BDR_MASK (0xFFU) 1055 #define NETC_F3_SI1_SICAPR0_NUM_TX_BDR_SHIFT (0U) 1056 #define NETC_F3_SI1_SICAPR0_NUM_TX_BDR_WIDTH (8U) 1057 #define NETC_F3_SI1_SICAPR0_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICAPR0_NUM_TX_BDR_SHIFT)) & NETC_F3_SI1_SICAPR0_NUM_TX_BDR_MASK) 1058 1059 #define NETC_F3_SI1_SICAPR0_NUM_RX_BDR_MASK (0xFF0000U) 1060 #define NETC_F3_SI1_SICAPR0_NUM_RX_BDR_SHIFT (16U) 1061 #define NETC_F3_SI1_SICAPR0_NUM_RX_BDR_WIDTH (8U) 1062 #define NETC_F3_SI1_SICAPR0_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICAPR0_NUM_RX_BDR_SHIFT)) & NETC_F3_SI1_SICAPR0_NUM_RX_BDR_MASK) 1063 /*! @} */ 1064 1065 /*! @name SICAPR1 - Station interface capability register 1 */ 1066 /*! @{ */ 1067 1068 #define NETC_F3_SI1_SICAPR1_NUM_RX_GRP_MASK (0xFF0000U) 1069 #define NETC_F3_SI1_SICAPR1_NUM_RX_GRP_SHIFT (16U) 1070 #define NETC_F3_SI1_SICAPR1_NUM_RX_GRP_WIDTH (8U) 1071 #define NETC_F3_SI1_SICAPR1_NUM_RX_GRP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICAPR1_NUM_RX_GRP_SHIFT)) & NETC_F3_SI1_SICAPR1_NUM_RX_GRP_MASK) 1072 /*! @} */ 1073 1074 /*! @name SICAPR2 - Station interface capability register 2 */ 1075 /*! @{ */ 1076 1077 #define NETC_F3_SI1_SICAPR2_VTP_MASK (0xFU) 1078 #define NETC_F3_SI1_SICAPR2_VTP_SHIFT (0U) 1079 #define NETC_F3_SI1_SICAPR2_VTP_WIDTH (4U) 1080 #define NETC_F3_SI1_SICAPR2_VTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICAPR2_VTP_SHIFT)) & NETC_F3_SI1_SICAPR2_VTP_MASK) 1081 /*! @} */ 1082 1083 /*! @name VSIIER - Virtual station interface interrupt enable register */ 1084 /*! @{ */ 1085 1086 #define NETC_F3_SI1_VSIIER_MSIE_MASK (0x100U) 1087 #define NETC_F3_SI1_VSIIER_MSIE_SHIFT (8U) 1088 #define NETC_F3_SI1_VSIIER_MSIE_WIDTH (1U) 1089 #define NETC_F3_SI1_VSIIER_MSIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIIER_MSIE_SHIFT)) & NETC_F3_SI1_VSIIER_MSIE_MASK) 1090 1091 #define NETC_F3_SI1_VSIIER_MRIE_MASK (0x200U) 1092 #define NETC_F3_SI1_VSIIER_MRIE_SHIFT (9U) 1093 #define NETC_F3_SI1_VSIIER_MRIE_WIDTH (1U) 1094 #define NETC_F3_SI1_VSIIER_MRIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIIER_MRIE_SHIFT)) & NETC_F3_SI1_VSIIER_MRIE_MASK) 1095 /*! @} */ 1096 1097 /*! @name VSIIDR - Virtual station interface interrupt detect register */ 1098 /*! @{ */ 1099 1100 #define NETC_F3_SI1_VSIIDR_TXR_MASK (0x1U) 1101 #define NETC_F3_SI1_VSIIDR_TXR_SHIFT (0U) 1102 #define NETC_F3_SI1_VSIIDR_TXR_WIDTH (1U) 1103 #define NETC_F3_SI1_VSIIDR_TXR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIIDR_TXR_SHIFT)) & NETC_F3_SI1_VSIIDR_TXR_MASK) 1104 1105 #define NETC_F3_SI1_VSIIDR_MS_MASK (0x100U) 1106 #define NETC_F3_SI1_VSIIDR_MS_SHIFT (8U) 1107 #define NETC_F3_SI1_VSIIDR_MS_WIDTH (1U) 1108 #define NETC_F3_SI1_VSIIDR_MS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIIDR_MS_SHIFT)) & NETC_F3_SI1_VSIIDR_MS_MASK) 1109 1110 #define NETC_F3_SI1_VSIIDR_MR_MASK (0x200U) 1111 #define NETC_F3_SI1_VSIIDR_MR_SHIFT (9U) 1112 #define NETC_F3_SI1_VSIIDR_MR_WIDTH (1U) 1113 #define NETC_F3_SI1_VSIIDR_MR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIIDR_MR_SHIFT)) & NETC_F3_SI1_VSIIDR_MR_MASK) 1114 1115 #define NETC_F3_SI1_VSIIDR_RXR_MASK (0x10000U) 1116 #define NETC_F3_SI1_VSIIDR_RXR_SHIFT (16U) 1117 #define NETC_F3_SI1_VSIIDR_RXR_WIDTH (1U) 1118 #define NETC_F3_SI1_VSIIDR_RXR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_VSIIDR_RXR_SHIFT)) & NETC_F3_SI1_VSIIDR_RXR_MASK) 1119 /*! @} */ 1120 1121 /*! @name SITXIDR0 - Station interface transmit interrupt detect register 0 */ 1122 /*! @{ */ 1123 1124 #define NETC_F3_SI1_SITXIDR0_TXT0_MASK (0x1U) 1125 #define NETC_F3_SI1_SITXIDR0_TXT0_SHIFT (0U) 1126 #define NETC_F3_SI1_SITXIDR0_TXT0_WIDTH (1U) 1127 #define NETC_F3_SI1_SITXIDR0_TXT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT0_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT0_MASK) 1128 1129 #define NETC_F3_SI1_SITXIDR0_TXT1_MASK (0x2U) 1130 #define NETC_F3_SI1_SITXIDR0_TXT1_SHIFT (1U) 1131 #define NETC_F3_SI1_SITXIDR0_TXT1_WIDTH (1U) 1132 #define NETC_F3_SI1_SITXIDR0_TXT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT1_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT1_MASK) 1133 1134 #define NETC_F3_SI1_SITXIDR0_TXT2_MASK (0x4U) 1135 #define NETC_F3_SI1_SITXIDR0_TXT2_SHIFT (2U) 1136 #define NETC_F3_SI1_SITXIDR0_TXT2_WIDTH (1U) 1137 #define NETC_F3_SI1_SITXIDR0_TXT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT2_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT2_MASK) 1138 1139 #define NETC_F3_SI1_SITXIDR0_TXT3_MASK (0x8U) 1140 #define NETC_F3_SI1_SITXIDR0_TXT3_SHIFT (3U) 1141 #define NETC_F3_SI1_SITXIDR0_TXT3_WIDTH (1U) 1142 #define NETC_F3_SI1_SITXIDR0_TXT3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT3_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT3_MASK) 1143 1144 #define NETC_F3_SI1_SITXIDR0_TXT4_MASK (0x10U) 1145 #define NETC_F3_SI1_SITXIDR0_TXT4_SHIFT (4U) 1146 #define NETC_F3_SI1_SITXIDR0_TXT4_WIDTH (1U) 1147 #define NETC_F3_SI1_SITXIDR0_TXT4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT4_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT4_MASK) 1148 1149 #define NETC_F3_SI1_SITXIDR0_TXT5_MASK (0x20U) 1150 #define NETC_F3_SI1_SITXIDR0_TXT5_SHIFT (5U) 1151 #define NETC_F3_SI1_SITXIDR0_TXT5_WIDTH (1U) 1152 #define NETC_F3_SI1_SITXIDR0_TXT5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT5_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT5_MASK) 1153 1154 #define NETC_F3_SI1_SITXIDR0_TXT6_MASK (0x40U) 1155 #define NETC_F3_SI1_SITXIDR0_TXT6_SHIFT (6U) 1156 #define NETC_F3_SI1_SITXIDR0_TXT6_WIDTH (1U) 1157 #define NETC_F3_SI1_SITXIDR0_TXT6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT6_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT6_MASK) 1158 1159 #define NETC_F3_SI1_SITXIDR0_TXT7_MASK (0x80U) 1160 #define NETC_F3_SI1_SITXIDR0_TXT7_SHIFT (7U) 1161 #define NETC_F3_SI1_SITXIDR0_TXT7_WIDTH (1U) 1162 #define NETC_F3_SI1_SITXIDR0_TXT7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT7_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT7_MASK) 1163 1164 #define NETC_F3_SI1_SITXIDR0_TXT8_MASK (0x100U) 1165 #define NETC_F3_SI1_SITXIDR0_TXT8_SHIFT (8U) 1166 #define NETC_F3_SI1_SITXIDR0_TXT8_WIDTH (1U) 1167 #define NETC_F3_SI1_SITXIDR0_TXT8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT8_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT8_MASK) 1168 1169 #define NETC_F3_SI1_SITXIDR0_TXT9_MASK (0x200U) 1170 #define NETC_F3_SI1_SITXIDR0_TXT9_SHIFT (9U) 1171 #define NETC_F3_SI1_SITXIDR0_TXT9_WIDTH (1U) 1172 #define NETC_F3_SI1_SITXIDR0_TXT9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT9_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT9_MASK) 1173 1174 #define NETC_F3_SI1_SITXIDR0_TXT10_MASK (0x400U) 1175 #define NETC_F3_SI1_SITXIDR0_TXT10_SHIFT (10U) 1176 #define NETC_F3_SI1_SITXIDR0_TXT10_WIDTH (1U) 1177 #define NETC_F3_SI1_SITXIDR0_TXT10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT10_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT10_MASK) 1178 1179 #define NETC_F3_SI1_SITXIDR0_TXT11_MASK (0x800U) 1180 #define NETC_F3_SI1_SITXIDR0_TXT11_SHIFT (11U) 1181 #define NETC_F3_SI1_SITXIDR0_TXT11_WIDTH (1U) 1182 #define NETC_F3_SI1_SITXIDR0_TXT11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT11_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT11_MASK) 1183 1184 #define NETC_F3_SI1_SITXIDR0_TXT12_MASK (0x1000U) 1185 #define NETC_F3_SI1_SITXIDR0_TXT12_SHIFT (12U) 1186 #define NETC_F3_SI1_SITXIDR0_TXT12_WIDTH (1U) 1187 #define NETC_F3_SI1_SITXIDR0_TXT12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT12_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT12_MASK) 1188 1189 #define NETC_F3_SI1_SITXIDR0_TXT13_MASK (0x2000U) 1190 #define NETC_F3_SI1_SITXIDR0_TXT13_SHIFT (13U) 1191 #define NETC_F3_SI1_SITXIDR0_TXT13_WIDTH (1U) 1192 #define NETC_F3_SI1_SITXIDR0_TXT13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT13_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT13_MASK) 1193 1194 #define NETC_F3_SI1_SITXIDR0_TXT14_MASK (0x4000U) 1195 #define NETC_F3_SI1_SITXIDR0_TXT14_SHIFT (14U) 1196 #define NETC_F3_SI1_SITXIDR0_TXT14_WIDTH (1U) 1197 #define NETC_F3_SI1_SITXIDR0_TXT14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT14_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT14_MASK) 1198 1199 #define NETC_F3_SI1_SITXIDR0_TXT15_MASK (0x8000U) 1200 #define NETC_F3_SI1_SITXIDR0_TXT15_SHIFT (15U) 1201 #define NETC_F3_SI1_SITXIDR0_TXT15_WIDTH (1U) 1202 #define NETC_F3_SI1_SITXIDR0_TXT15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXT15_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXT15_MASK) 1203 1204 #define NETC_F3_SI1_SITXIDR0_TXF0_MASK (0x10000U) 1205 #define NETC_F3_SI1_SITXIDR0_TXF0_SHIFT (16U) 1206 #define NETC_F3_SI1_SITXIDR0_TXF0_WIDTH (1U) 1207 #define NETC_F3_SI1_SITXIDR0_TXF0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF0_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF0_MASK) 1208 1209 #define NETC_F3_SI1_SITXIDR0_TXF1_MASK (0x20000U) 1210 #define NETC_F3_SI1_SITXIDR0_TXF1_SHIFT (17U) 1211 #define NETC_F3_SI1_SITXIDR0_TXF1_WIDTH (1U) 1212 #define NETC_F3_SI1_SITXIDR0_TXF1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF1_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF1_MASK) 1213 1214 #define NETC_F3_SI1_SITXIDR0_TXF2_MASK (0x40000U) 1215 #define NETC_F3_SI1_SITXIDR0_TXF2_SHIFT (18U) 1216 #define NETC_F3_SI1_SITXIDR0_TXF2_WIDTH (1U) 1217 #define NETC_F3_SI1_SITXIDR0_TXF2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF2_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF2_MASK) 1218 1219 #define NETC_F3_SI1_SITXIDR0_TXF3_MASK (0x80000U) 1220 #define NETC_F3_SI1_SITXIDR0_TXF3_SHIFT (19U) 1221 #define NETC_F3_SI1_SITXIDR0_TXF3_WIDTH (1U) 1222 #define NETC_F3_SI1_SITXIDR0_TXF3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF3_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF3_MASK) 1223 1224 #define NETC_F3_SI1_SITXIDR0_TXF4_MASK (0x100000U) 1225 #define NETC_F3_SI1_SITXIDR0_TXF4_SHIFT (20U) 1226 #define NETC_F3_SI1_SITXIDR0_TXF4_WIDTH (1U) 1227 #define NETC_F3_SI1_SITXIDR0_TXF4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF4_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF4_MASK) 1228 1229 #define NETC_F3_SI1_SITXIDR0_TXF5_MASK (0x200000U) 1230 #define NETC_F3_SI1_SITXIDR0_TXF5_SHIFT (21U) 1231 #define NETC_F3_SI1_SITXIDR0_TXF5_WIDTH (1U) 1232 #define NETC_F3_SI1_SITXIDR0_TXF5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF5_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF5_MASK) 1233 1234 #define NETC_F3_SI1_SITXIDR0_TXF6_MASK (0x400000U) 1235 #define NETC_F3_SI1_SITXIDR0_TXF6_SHIFT (22U) 1236 #define NETC_F3_SI1_SITXIDR0_TXF6_WIDTH (1U) 1237 #define NETC_F3_SI1_SITXIDR0_TXF6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF6_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF6_MASK) 1238 1239 #define NETC_F3_SI1_SITXIDR0_TXF7_MASK (0x800000U) 1240 #define NETC_F3_SI1_SITXIDR0_TXF7_SHIFT (23U) 1241 #define NETC_F3_SI1_SITXIDR0_TXF7_WIDTH (1U) 1242 #define NETC_F3_SI1_SITXIDR0_TXF7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF7_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF7_MASK) 1243 1244 #define NETC_F3_SI1_SITXIDR0_TXF8_MASK (0x1000000U) 1245 #define NETC_F3_SI1_SITXIDR0_TXF8_SHIFT (24U) 1246 #define NETC_F3_SI1_SITXIDR0_TXF8_WIDTH (1U) 1247 #define NETC_F3_SI1_SITXIDR0_TXF8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF8_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF8_MASK) 1248 1249 #define NETC_F3_SI1_SITXIDR0_TXF9_MASK (0x2000000U) 1250 #define NETC_F3_SI1_SITXIDR0_TXF9_SHIFT (25U) 1251 #define NETC_F3_SI1_SITXIDR0_TXF9_WIDTH (1U) 1252 #define NETC_F3_SI1_SITXIDR0_TXF9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF9_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF9_MASK) 1253 1254 #define NETC_F3_SI1_SITXIDR0_TXF10_MASK (0x4000000U) 1255 #define NETC_F3_SI1_SITXIDR0_TXF10_SHIFT (26U) 1256 #define NETC_F3_SI1_SITXIDR0_TXF10_WIDTH (1U) 1257 #define NETC_F3_SI1_SITXIDR0_TXF10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF10_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF10_MASK) 1258 1259 #define NETC_F3_SI1_SITXIDR0_TXF11_MASK (0x8000000U) 1260 #define NETC_F3_SI1_SITXIDR0_TXF11_SHIFT (27U) 1261 #define NETC_F3_SI1_SITXIDR0_TXF11_WIDTH (1U) 1262 #define NETC_F3_SI1_SITXIDR0_TXF11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF11_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF11_MASK) 1263 1264 #define NETC_F3_SI1_SITXIDR0_TXF12_MASK (0x10000000U) 1265 #define NETC_F3_SI1_SITXIDR0_TXF12_SHIFT (28U) 1266 #define NETC_F3_SI1_SITXIDR0_TXF12_WIDTH (1U) 1267 #define NETC_F3_SI1_SITXIDR0_TXF12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF12_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF12_MASK) 1268 1269 #define NETC_F3_SI1_SITXIDR0_TXF13_MASK (0x20000000U) 1270 #define NETC_F3_SI1_SITXIDR0_TXF13_SHIFT (29U) 1271 #define NETC_F3_SI1_SITXIDR0_TXF13_WIDTH (1U) 1272 #define NETC_F3_SI1_SITXIDR0_TXF13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF13_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF13_MASK) 1273 1274 #define NETC_F3_SI1_SITXIDR0_TXF14_MASK (0x40000000U) 1275 #define NETC_F3_SI1_SITXIDR0_TXF14_SHIFT (30U) 1276 #define NETC_F3_SI1_SITXIDR0_TXF14_WIDTH (1U) 1277 #define NETC_F3_SI1_SITXIDR0_TXF14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF14_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF14_MASK) 1278 1279 #define NETC_F3_SI1_SITXIDR0_TXF15_MASK (0x80000000U) 1280 #define NETC_F3_SI1_SITXIDR0_TXF15_SHIFT (31U) 1281 #define NETC_F3_SI1_SITXIDR0_TXF15_WIDTH (1U) 1282 #define NETC_F3_SI1_SITXIDR0_TXF15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR0_TXF15_SHIFT)) & NETC_F3_SI1_SITXIDR0_TXF15_MASK) 1283 /*! @} */ 1284 1285 /*! @name SITXIDR1 - Station interface transmit interrupt detect register 1 */ 1286 /*! @{ */ 1287 1288 #define NETC_F3_SI1_SITXIDR1_TXT16_MASK (0x1U) 1289 #define NETC_F3_SI1_SITXIDR1_TXT16_SHIFT (0U) 1290 #define NETC_F3_SI1_SITXIDR1_TXT16_WIDTH (1U) 1291 #define NETC_F3_SI1_SITXIDR1_TXT16(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR1_TXT16_SHIFT)) & NETC_F3_SI1_SITXIDR1_TXT16_MASK) 1292 1293 #define NETC_F3_SI1_SITXIDR1_TXT17_MASK (0x2U) 1294 #define NETC_F3_SI1_SITXIDR1_TXT17_SHIFT (1U) 1295 #define NETC_F3_SI1_SITXIDR1_TXT17_WIDTH (1U) 1296 #define NETC_F3_SI1_SITXIDR1_TXT17(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR1_TXT17_SHIFT)) & NETC_F3_SI1_SITXIDR1_TXT17_MASK) 1297 1298 #define NETC_F3_SI1_SITXIDR1_TXF16_MASK (0x10000U) 1299 #define NETC_F3_SI1_SITXIDR1_TXF16_SHIFT (16U) 1300 #define NETC_F3_SI1_SITXIDR1_TXF16_WIDTH (1U) 1301 #define NETC_F3_SI1_SITXIDR1_TXF16(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR1_TXF16_SHIFT)) & NETC_F3_SI1_SITXIDR1_TXF16_MASK) 1302 1303 #define NETC_F3_SI1_SITXIDR1_TXF17_MASK (0x20000U) 1304 #define NETC_F3_SI1_SITXIDR1_TXF17_SHIFT (17U) 1305 #define NETC_F3_SI1_SITXIDR1_TXF17_WIDTH (1U) 1306 #define NETC_F3_SI1_SITXIDR1_TXF17(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITXIDR1_TXF17_SHIFT)) & NETC_F3_SI1_SITXIDR1_TXF17_MASK) 1307 /*! @} */ 1308 1309 /*! @name SIRXIDR0 - Station interface receive interrupt detect register 0 */ 1310 /*! @{ */ 1311 1312 #define NETC_F3_SI1_SIRXIDR0_RX0_MASK (0x1U) 1313 #define NETC_F3_SI1_SIRXIDR0_RX0_SHIFT (0U) 1314 #define NETC_F3_SI1_SIRXIDR0_RX0_WIDTH (1U) 1315 #define NETC_F3_SI1_SIRXIDR0_RX0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX0_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX0_MASK) 1316 1317 #define NETC_F3_SI1_SIRXIDR0_RX1_MASK (0x2U) 1318 #define NETC_F3_SI1_SIRXIDR0_RX1_SHIFT (1U) 1319 #define NETC_F3_SI1_SIRXIDR0_RX1_WIDTH (1U) 1320 #define NETC_F3_SI1_SIRXIDR0_RX1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX1_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX1_MASK) 1321 1322 #define NETC_F3_SI1_SIRXIDR0_RX2_MASK (0x4U) 1323 #define NETC_F3_SI1_SIRXIDR0_RX2_SHIFT (2U) 1324 #define NETC_F3_SI1_SIRXIDR0_RX2_WIDTH (1U) 1325 #define NETC_F3_SI1_SIRXIDR0_RX2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX2_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX2_MASK) 1326 1327 #define NETC_F3_SI1_SIRXIDR0_RX3_MASK (0x8U) 1328 #define NETC_F3_SI1_SIRXIDR0_RX3_SHIFT (3U) 1329 #define NETC_F3_SI1_SIRXIDR0_RX3_WIDTH (1U) 1330 #define NETC_F3_SI1_SIRXIDR0_RX3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX3_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX3_MASK) 1331 1332 #define NETC_F3_SI1_SIRXIDR0_RX4_MASK (0x10U) 1333 #define NETC_F3_SI1_SIRXIDR0_RX4_SHIFT (4U) 1334 #define NETC_F3_SI1_SIRXIDR0_RX4_WIDTH (1U) 1335 #define NETC_F3_SI1_SIRXIDR0_RX4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX4_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX4_MASK) 1336 1337 #define NETC_F3_SI1_SIRXIDR0_RX5_MASK (0x20U) 1338 #define NETC_F3_SI1_SIRXIDR0_RX5_SHIFT (5U) 1339 #define NETC_F3_SI1_SIRXIDR0_RX5_WIDTH (1U) 1340 #define NETC_F3_SI1_SIRXIDR0_RX5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX5_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX5_MASK) 1341 1342 #define NETC_F3_SI1_SIRXIDR0_RX6_MASK (0x40U) 1343 #define NETC_F3_SI1_SIRXIDR0_RX6_SHIFT (6U) 1344 #define NETC_F3_SI1_SIRXIDR0_RX6_WIDTH (1U) 1345 #define NETC_F3_SI1_SIRXIDR0_RX6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX6_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX6_MASK) 1346 1347 #define NETC_F3_SI1_SIRXIDR0_RX7_MASK (0x80U) 1348 #define NETC_F3_SI1_SIRXIDR0_RX7_SHIFT (7U) 1349 #define NETC_F3_SI1_SIRXIDR0_RX7_WIDTH (1U) 1350 #define NETC_F3_SI1_SIRXIDR0_RX7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX7_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX7_MASK) 1351 1352 #define NETC_F3_SI1_SIRXIDR0_RX8_MASK (0x100U) 1353 #define NETC_F3_SI1_SIRXIDR0_RX8_SHIFT (8U) 1354 #define NETC_F3_SI1_SIRXIDR0_RX8_WIDTH (1U) 1355 #define NETC_F3_SI1_SIRXIDR0_RX8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX8_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX8_MASK) 1356 1357 #define NETC_F3_SI1_SIRXIDR0_RX9_MASK (0x200U) 1358 #define NETC_F3_SI1_SIRXIDR0_RX9_SHIFT (9U) 1359 #define NETC_F3_SI1_SIRXIDR0_RX9_WIDTH (1U) 1360 #define NETC_F3_SI1_SIRXIDR0_RX9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX9_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX9_MASK) 1361 1362 #define NETC_F3_SI1_SIRXIDR0_RX10_MASK (0x400U) 1363 #define NETC_F3_SI1_SIRXIDR0_RX10_SHIFT (10U) 1364 #define NETC_F3_SI1_SIRXIDR0_RX10_WIDTH (1U) 1365 #define NETC_F3_SI1_SIRXIDR0_RX10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX10_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX10_MASK) 1366 1367 #define NETC_F3_SI1_SIRXIDR0_RX11_MASK (0x800U) 1368 #define NETC_F3_SI1_SIRXIDR0_RX11_SHIFT (11U) 1369 #define NETC_F3_SI1_SIRXIDR0_RX11_WIDTH (1U) 1370 #define NETC_F3_SI1_SIRXIDR0_RX11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX11_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX11_MASK) 1371 1372 #define NETC_F3_SI1_SIRXIDR0_RX12_MASK (0x1000U) 1373 #define NETC_F3_SI1_SIRXIDR0_RX12_SHIFT (12U) 1374 #define NETC_F3_SI1_SIRXIDR0_RX12_WIDTH (1U) 1375 #define NETC_F3_SI1_SIRXIDR0_RX12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX12_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX12_MASK) 1376 1377 #define NETC_F3_SI1_SIRXIDR0_RX13_MASK (0x2000U) 1378 #define NETC_F3_SI1_SIRXIDR0_RX13_SHIFT (13U) 1379 #define NETC_F3_SI1_SIRXIDR0_RX13_WIDTH (1U) 1380 #define NETC_F3_SI1_SIRXIDR0_RX13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX13_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX13_MASK) 1381 1382 #define NETC_F3_SI1_SIRXIDR0_RX14_MASK (0x4000U) 1383 #define NETC_F3_SI1_SIRXIDR0_RX14_SHIFT (14U) 1384 #define NETC_F3_SI1_SIRXIDR0_RX14_WIDTH (1U) 1385 #define NETC_F3_SI1_SIRXIDR0_RX14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX14_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX14_MASK) 1386 1387 #define NETC_F3_SI1_SIRXIDR0_RX15_MASK (0x8000U) 1388 #define NETC_F3_SI1_SIRXIDR0_RX15_SHIFT (15U) 1389 #define NETC_F3_SI1_SIRXIDR0_RX15_WIDTH (1U) 1390 #define NETC_F3_SI1_SIRXIDR0_RX15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR0_RX15_SHIFT)) & NETC_F3_SI1_SIRXIDR0_RX15_MASK) 1391 /*! @} */ 1392 1393 /*! @name SIRXIDR1 - Station interface receive interrupt detect register 1 */ 1394 /*! @{ */ 1395 1396 #define NETC_F3_SI1_SIRXIDR1_RX16_MASK (0x1U) 1397 #define NETC_F3_SI1_SIRXIDR1_RX16_SHIFT (0U) 1398 #define NETC_F3_SI1_SIRXIDR1_RX16_WIDTH (1U) 1399 #define NETC_F3_SI1_SIRXIDR1_RX16(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR1_RX16_SHIFT)) & NETC_F3_SI1_SIRXIDR1_RX16_MASK) 1400 1401 #define NETC_F3_SI1_SIRXIDR1_RX17_MASK (0x2U) 1402 #define NETC_F3_SI1_SIRXIDR1_RX17_SHIFT (1U) 1403 #define NETC_F3_SI1_SIRXIDR1_RX17_WIDTH (1U) 1404 #define NETC_F3_SI1_SIRXIDR1_RX17(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRXIDR1_RX17_SHIFT)) & NETC_F3_SI1_SIRXIDR1_RX17_MASK) 1405 /*! @} */ 1406 1407 /*! @name SIMSIVR - Station interface MSI-X vector register */ 1408 /*! @{ */ 1409 1410 #define NETC_F3_SI1_SIMSIVR_VECTOR_MASK (0x3FU) 1411 #define NETC_F3_SI1_SIMSIVR_VECTOR_SHIFT (0U) 1412 #define NETC_F3_SI1_SIMSIVR_VECTOR_WIDTH (6U) 1413 #define NETC_F3_SI1_SIMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMSIVR_VECTOR_SHIFT)) & NETC_F3_SI1_SIMSIVR_VECTOR_MASK) 1414 /*! @} */ 1415 1416 /*! @name SICMSIVR - Station interface command MSI-X vector register */ 1417 /*! @{ */ 1418 1419 #define NETC_F3_SI1_SICMSIVR_VECTOR_MASK (0x3FU) 1420 #define NETC_F3_SI1_SICMSIVR_VECTOR_SHIFT (0U) 1421 #define NETC_F3_SI1_SICMSIVR_VECTOR_WIDTH (6U) 1422 #define NETC_F3_SI1_SICMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICMSIVR_VECTOR_SHIFT)) & NETC_F3_SI1_SICMSIVR_VECTOR_MASK) 1423 /*! @} */ 1424 1425 /*! @name SITMRIER - Station interface timer interrupt enable register */ 1426 /*! @{ */ 1427 1428 #define NETC_F3_SI1_SITMRIER_SYNCE_MASK (0x1U) 1429 #define NETC_F3_SI1_SITMRIER_SYNCE_SHIFT (0U) 1430 #define NETC_F3_SI1_SITMRIER_SYNCE_WIDTH (1U) 1431 #define NETC_F3_SI1_SITMRIER_SYNCE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITMRIER_SYNCE_SHIFT)) & NETC_F3_SI1_SITMRIER_SYNCE_MASK) 1432 /*! @} */ 1433 1434 /*! @name SITMRIDR - Station interface timer interrupt detect register */ 1435 /*! @{ */ 1436 1437 #define NETC_F3_SI1_SITMRIDR_SYNC_MASK (0x1U) 1438 #define NETC_F3_SI1_SITMRIDR_SYNC_SHIFT (0U) 1439 #define NETC_F3_SI1_SITMRIDR_SYNC_WIDTH (1U) 1440 #define NETC_F3_SI1_SITMRIDR_SYNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITMRIDR_SYNC_SHIFT)) & NETC_F3_SI1_SITMRIDR_SYNC_MASK) 1441 /*! @} */ 1442 1443 /*! @name SITMRMSIVR - Station interface timer MSI-X vector register */ 1444 /*! @{ */ 1445 1446 #define NETC_F3_SI1_SITMRMSIVR_VECTOR_MASK (0x3FU) 1447 #define NETC_F3_SI1_SITMRMSIVR_VECTOR_SHIFT (0U) 1448 #define NETC_F3_SI1_SITMRMSIVR_VECTOR_WIDTH (6U) 1449 #define NETC_F3_SI1_SITMRMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SITMRMSIVR_VECTOR_SHIFT)) & NETC_F3_SI1_SITMRMSIVR_VECTOR_MASK) 1450 /*! @} */ 1451 1452 /*! @name SIMSITRVR - Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 17 vector register */ 1453 /*! @{ */ 1454 1455 #define NETC_F3_SI1_SIMSITRVR_VECTOR_MASK (0x3FU) 1456 #define NETC_F3_SI1_SIMSITRVR_VECTOR_SHIFT (0U) 1457 #define NETC_F3_SI1_SIMSITRVR_VECTOR_WIDTH (6U) 1458 #define NETC_F3_SI1_SIMSITRVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMSITRVR_VECTOR_SHIFT)) & NETC_F3_SI1_SIMSITRVR_VECTOR_MASK) 1459 /*! @} */ 1460 1461 /*! @name SIMSIRRVR - Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 17 vector register */ 1462 /*! @{ */ 1463 1464 #define NETC_F3_SI1_SIMSIRRVR_VECTOR_MASK (0x3FU) 1465 #define NETC_F3_SI1_SIMSIRRVR_VECTOR_SHIFT (0U) 1466 #define NETC_F3_SI1_SIMSIRRVR_VECTOR_WIDTH (6U) 1467 #define NETC_F3_SI1_SIMSIRRVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMSIRRVR_VECTOR_SHIFT)) & NETC_F3_SI1_SIMSIRRVR_VECTOR_MASK) 1468 /*! @} */ 1469 1470 /*! @name SICMECR - Station interface correctable memory error configuration register */ 1471 /*! @{ */ 1472 1473 #define NETC_F3_SI1_SICMECR_THRESHOLD_MASK (0xFFU) 1474 #define NETC_F3_SI1_SICMECR_THRESHOLD_SHIFT (0U) 1475 #define NETC_F3_SI1_SICMECR_THRESHOLD_WIDTH (8U) 1476 #define NETC_F3_SI1_SICMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICMECR_THRESHOLD_SHIFT)) & NETC_F3_SI1_SICMECR_THRESHOLD_MASK) 1477 /*! @} */ 1478 1479 /*! @name SICMESR - Station interface correctable memory error status register */ 1480 /*! @{ */ 1481 1482 #define NETC_F3_SI1_SICMESR_MEM_ID_MASK (0x1F0000U) 1483 #define NETC_F3_SI1_SICMESR_MEM_ID_SHIFT (16U) 1484 #define NETC_F3_SI1_SICMESR_MEM_ID_WIDTH (5U) 1485 #define NETC_F3_SI1_SICMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICMESR_MEM_ID_SHIFT)) & NETC_F3_SI1_SICMESR_MEM_ID_MASK) 1486 1487 #define NETC_F3_SI1_SICMESR_SBEE_MASK (0x80000000U) 1488 #define NETC_F3_SI1_SICMESR_SBEE_SHIFT (31U) 1489 #define NETC_F3_SI1_SICMESR_SBEE_WIDTH (1U) 1490 #define NETC_F3_SI1_SICMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICMESR_SBEE_SHIFT)) & NETC_F3_SI1_SICMESR_SBEE_MASK) 1491 /*! @} */ 1492 1493 /*! @name SICMECTR - Station interface correctable memory error count register */ 1494 /*! @{ */ 1495 1496 #define NETC_F3_SI1_SICMECTR_COUNT_MASK (0xFFU) 1497 #define NETC_F3_SI1_SICMECTR_COUNT_SHIFT (0U) 1498 #define NETC_F3_SI1_SICMECTR_COUNT_WIDTH (8U) 1499 #define NETC_F3_SI1_SICMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SICMECTR_COUNT_SHIFT)) & NETC_F3_SI1_SICMECTR_COUNT_MASK) 1500 /*! @} */ 1501 1502 /*! @name SIUPECR - Station interface uncorrectable programming error configuration register */ 1503 /*! @{ */ 1504 1505 #define NETC_F3_SI1_SIUPECR_RD_MASK (0x80000000U) 1506 #define NETC_F3_SI1_SIUPECR_RD_SHIFT (31U) 1507 #define NETC_F3_SI1_SIUPECR_RD_WIDTH (1U) 1508 #define NETC_F3_SI1_SIUPECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPECR_RD_SHIFT)) & NETC_F3_SI1_SIUPECR_RD_MASK) 1509 /*! @} */ 1510 1511 /*! @name SIUPESR - Station interface uncorrectable programming error status register */ 1512 /*! @{ */ 1513 1514 #define NETC_F3_SI1_SIUPESR_DROP_SI_EN_MASK (0x1U) 1515 #define NETC_F3_SI1_SIUPESR_DROP_SI_EN_SHIFT (0U) 1516 #define NETC_F3_SI1_SIUPESR_DROP_SI_EN_WIDTH (1U) 1517 #define NETC_F3_SI1_SIUPESR_DROP_SI_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPESR_DROP_SI_EN_SHIFT)) & NETC_F3_SI1_SIUPESR_DROP_SI_EN_MASK) 1518 1519 #define NETC_F3_SI1_SIUPESR_DROP_RING_EN_MASK (0x2U) 1520 #define NETC_F3_SI1_SIUPESR_DROP_RING_EN_SHIFT (1U) 1521 #define NETC_F3_SI1_SIUPESR_DROP_RING_EN_WIDTH (1U) 1522 #define NETC_F3_SI1_SIUPESR_DROP_RING_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPESR_DROP_RING_EN_SHIFT)) & NETC_F3_SI1_SIUPESR_DROP_RING_EN_MASK) 1523 1524 #define NETC_F3_SI1_SIUPESR_DROP_GRP_SEL_MASK (0x4U) 1525 #define NETC_F3_SI1_SIUPESR_DROP_GRP_SEL_SHIFT (2U) 1526 #define NETC_F3_SI1_SIUPESR_DROP_GRP_SEL_WIDTH (1U) 1527 #define NETC_F3_SI1_SIUPESR_DROP_GRP_SEL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPESR_DROP_GRP_SEL_SHIFT)) & NETC_F3_SI1_SIUPESR_DROP_GRP_SEL_MASK) 1528 1529 #define NETC_F3_SI1_SIUPESR_DROP_RING_SEL_MASK (0x8U) 1530 #define NETC_F3_SI1_SIUPESR_DROP_RING_SEL_SHIFT (3U) 1531 #define NETC_F3_SI1_SIUPESR_DROP_RING_SEL_WIDTH (1U) 1532 #define NETC_F3_SI1_SIUPESR_DROP_RING_SEL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPESR_DROP_RING_SEL_SHIFT)) & NETC_F3_SI1_SIUPESR_DROP_RING_SEL_MASK) 1533 1534 #define NETC_F3_SI1_SIUPESR_M_MASK (0x40000000U) 1535 #define NETC_F3_SI1_SIUPESR_M_SHIFT (30U) 1536 #define NETC_F3_SI1_SIUPESR_M_WIDTH (1U) 1537 #define NETC_F3_SI1_SIUPESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPESR_M_SHIFT)) & NETC_F3_SI1_SIUPESR_M_MASK) 1538 1539 #define NETC_F3_SI1_SIUPESR_PE_MASK (0x80000000U) 1540 #define NETC_F3_SI1_SIUPESR_PE_SHIFT (31U) 1541 #define NETC_F3_SI1_SIUPESR_PE_WIDTH (1U) 1542 #define NETC_F3_SI1_SIUPESR_PE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPESR_PE_SHIFT)) & NETC_F3_SI1_SIUPESR_PE_MASK) 1543 /*! @} */ 1544 1545 /*! @name SIUPECTR - Station interface uncorrectable programming error count register */ 1546 /*! @{ */ 1547 1548 #define NETC_F3_SI1_SIUPECTR_COUNT_MASK (0xFFFFFFFFU) 1549 #define NETC_F3_SI1_SIUPECTR_COUNT_SHIFT (0U) 1550 #define NETC_F3_SI1_SIUPECTR_COUNT_WIDTH (32U) 1551 #define NETC_F3_SI1_SIUPECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUPECTR_COUNT_SHIFT)) & NETC_F3_SI1_SIUPECTR_COUNT_MASK) 1552 /*! @} */ 1553 1554 /*! @name SIUNSBECR - Station interface uncorrectable non-fatal system bus error configuration register */ 1555 /*! @{ */ 1556 1557 #define NETC_F3_SI1_SIUNSBECR_THRESHOLD_MASK (0xFFU) 1558 #define NETC_F3_SI1_SIUNSBECR_THRESHOLD_SHIFT (0U) 1559 #define NETC_F3_SI1_SIUNSBECR_THRESHOLD_WIDTH (8U) 1560 #define NETC_F3_SI1_SIUNSBECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNSBECR_THRESHOLD_SHIFT)) & NETC_F3_SI1_SIUNSBECR_THRESHOLD_MASK) 1561 /*! @} */ 1562 1563 /*! @name SIUNSBESR - Station interface uncorrectable non-fatal system bus error status register */ 1564 /*! @{ */ 1565 1566 #define NETC_F3_SI1_SIUNSBESR_SB_ID_MASK (0xFU) 1567 #define NETC_F3_SI1_SIUNSBESR_SB_ID_SHIFT (0U) 1568 #define NETC_F3_SI1_SIUNSBESR_SB_ID_WIDTH (4U) 1569 #define NETC_F3_SI1_SIUNSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNSBESR_SB_ID_SHIFT)) & NETC_F3_SI1_SIUNSBESR_SB_ID_MASK) 1570 1571 #define NETC_F3_SI1_SIUNSBESR_SBE_MASK (0x80000000U) 1572 #define NETC_F3_SI1_SIUNSBESR_SBE_SHIFT (31U) 1573 #define NETC_F3_SI1_SIUNSBESR_SBE_WIDTH (1U) 1574 #define NETC_F3_SI1_SIUNSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNSBESR_SBE_SHIFT)) & NETC_F3_SI1_SIUNSBESR_SBE_MASK) 1575 /*! @} */ 1576 1577 /*! @name SIUNSBECTR - Station interface uncorrectable non-fatal system bus error count register */ 1578 /*! @{ */ 1579 1580 #define NETC_F3_SI1_SIUNSBECTR_COUNT_MASK (0xFFU) 1581 #define NETC_F3_SI1_SIUNSBECTR_COUNT_SHIFT (0U) 1582 #define NETC_F3_SI1_SIUNSBECTR_COUNT_WIDTH (8U) 1583 #define NETC_F3_SI1_SIUNSBECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNSBECTR_COUNT_SHIFT)) & NETC_F3_SI1_SIUNSBECTR_COUNT_MASK) 1584 /*! @} */ 1585 1586 /*! @name SIUFSBECR - Station interface uncorrectable fatal system bus error configuration register */ 1587 /*! @{ */ 1588 1589 #define NETC_F3_SI1_SIUFSBECR_RD_MASK (0x80000000U) 1590 #define NETC_F3_SI1_SIUFSBECR_RD_SHIFT (31U) 1591 #define NETC_F3_SI1_SIUFSBECR_RD_WIDTH (1U) 1592 #define NETC_F3_SI1_SIUFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFSBECR_RD_SHIFT)) & NETC_F3_SI1_SIUFSBECR_RD_MASK) 1593 /*! @} */ 1594 1595 /*! @name SIUFSBESR - Station interface uncorrectable fatal system bus error status register */ 1596 /*! @{ */ 1597 1598 #define NETC_F3_SI1_SIUFSBESR_SB_ID_MASK (0xFU) 1599 #define NETC_F3_SI1_SIUFSBESR_SB_ID_SHIFT (0U) 1600 #define NETC_F3_SI1_SIUFSBESR_SB_ID_WIDTH (4U) 1601 #define NETC_F3_SI1_SIUFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFSBESR_SB_ID_SHIFT)) & NETC_F3_SI1_SIUFSBESR_SB_ID_MASK) 1602 1603 #define NETC_F3_SI1_SIUFSBESR_M_MASK (0x40000000U) 1604 #define NETC_F3_SI1_SIUFSBESR_M_SHIFT (30U) 1605 #define NETC_F3_SI1_SIUFSBESR_M_WIDTH (1U) 1606 #define NETC_F3_SI1_SIUFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFSBESR_M_SHIFT)) & NETC_F3_SI1_SIUFSBESR_M_MASK) 1607 1608 #define NETC_F3_SI1_SIUFSBESR_SBE_MASK (0x80000000U) 1609 #define NETC_F3_SI1_SIUFSBESR_SBE_SHIFT (31U) 1610 #define NETC_F3_SI1_SIUFSBESR_SBE_WIDTH (1U) 1611 #define NETC_F3_SI1_SIUFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFSBESR_SBE_SHIFT)) & NETC_F3_SI1_SIUFSBESR_SBE_MASK) 1612 /*! @} */ 1613 1614 /*! @name SIUNMECR - Station interface uncorrectable non-fatal memory error configuration register */ 1615 /*! @{ */ 1616 1617 #define NETC_F3_SI1_SIUNMECR_THRESHOLD_MASK (0xFFU) 1618 #define NETC_F3_SI1_SIUNMECR_THRESHOLD_SHIFT (0U) 1619 #define NETC_F3_SI1_SIUNMECR_THRESHOLD_WIDTH (8U) 1620 #define NETC_F3_SI1_SIUNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNMECR_THRESHOLD_SHIFT)) & NETC_F3_SI1_SIUNMECR_THRESHOLD_MASK) 1621 1622 #define NETC_F3_SI1_SIUNMECR_RD_MASK (0x80000000U) 1623 #define NETC_F3_SI1_SIUNMECR_RD_SHIFT (31U) 1624 #define NETC_F3_SI1_SIUNMECR_RD_WIDTH (1U) 1625 #define NETC_F3_SI1_SIUNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNMECR_RD_SHIFT)) & NETC_F3_SI1_SIUNMECR_RD_MASK) 1626 /*! @} */ 1627 1628 /*! @name SIUNMESR0 - Station interface uncorrectable non-fatal memory error status register 0 */ 1629 /*! @{ */ 1630 1631 #define NETC_F3_SI1_SIUNMESR0_SYNDROME_MASK (0x7FFU) 1632 #define NETC_F3_SI1_SIUNMESR0_SYNDROME_SHIFT (0U) 1633 #define NETC_F3_SI1_SIUNMESR0_SYNDROME_WIDTH (11U) 1634 #define NETC_F3_SI1_SIUNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNMESR0_SYNDROME_SHIFT)) & NETC_F3_SI1_SIUNMESR0_SYNDROME_MASK) 1635 1636 #define NETC_F3_SI1_SIUNMESR0_MEM_ID_MASK (0x1F0000U) 1637 #define NETC_F3_SI1_SIUNMESR0_MEM_ID_SHIFT (16U) 1638 #define NETC_F3_SI1_SIUNMESR0_MEM_ID_WIDTH (5U) 1639 #define NETC_F3_SI1_SIUNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNMESR0_MEM_ID_SHIFT)) & NETC_F3_SI1_SIUNMESR0_MEM_ID_MASK) 1640 1641 #define NETC_F3_SI1_SIUNMESR0_MBEE_MASK (0x80000000U) 1642 #define NETC_F3_SI1_SIUNMESR0_MBEE_SHIFT (31U) 1643 #define NETC_F3_SI1_SIUNMESR0_MBEE_WIDTH (1U) 1644 #define NETC_F3_SI1_SIUNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNMESR0_MBEE_SHIFT)) & NETC_F3_SI1_SIUNMESR0_MBEE_MASK) 1645 /*! @} */ 1646 1647 /*! @name SIUNMESR1 - Station interface uncorrectable non-fatal memory error status register 1 */ 1648 /*! @{ */ 1649 1650 #define NETC_F3_SI1_SIUNMESR1_ADDR_MASK (0xFFFFFFFFU) 1651 #define NETC_F3_SI1_SIUNMESR1_ADDR_SHIFT (0U) 1652 #define NETC_F3_SI1_SIUNMESR1_ADDR_WIDTH (32U) 1653 #define NETC_F3_SI1_SIUNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNMESR1_ADDR_SHIFT)) & NETC_F3_SI1_SIUNMESR1_ADDR_MASK) 1654 /*! @} */ 1655 1656 /*! @name SIUNMECTR - Station interface uncorrectable non-fatal memory error count register */ 1657 /*! @{ */ 1658 1659 #define NETC_F3_SI1_SIUNMECTR_COUNT_MASK (0xFFU) 1660 #define NETC_F3_SI1_SIUNMECTR_COUNT_SHIFT (0U) 1661 #define NETC_F3_SI1_SIUNMECTR_COUNT_WIDTH (8U) 1662 #define NETC_F3_SI1_SIUNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNMECTR_COUNT_SHIFT)) & NETC_F3_SI1_SIUNMECTR_COUNT_MASK) 1663 /*! @} */ 1664 1665 /*! @name SIUFMECR - Station interface uncorrectable fatal memory error configuration register */ 1666 /*! @{ */ 1667 1668 #define NETC_F3_SI1_SIUFMECR_RD_MASK (0x80000000U) 1669 #define NETC_F3_SI1_SIUFMECR_RD_SHIFT (31U) 1670 #define NETC_F3_SI1_SIUFMECR_RD_WIDTH (1U) 1671 #define NETC_F3_SI1_SIUFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFMECR_RD_SHIFT)) & NETC_F3_SI1_SIUFMECR_RD_MASK) 1672 /*! @} */ 1673 1674 /*! @name SIUFMESR0 - Station interface uncorrectable fatal memory error status register 0 */ 1675 /*! @{ */ 1676 1677 #define NETC_F3_SI1_SIUFMESR0_SYNDROME_MASK (0x7FFU) 1678 #define NETC_F3_SI1_SIUFMESR0_SYNDROME_SHIFT (0U) 1679 #define NETC_F3_SI1_SIUFMESR0_SYNDROME_WIDTH (11U) 1680 #define NETC_F3_SI1_SIUFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFMESR0_SYNDROME_SHIFT)) & NETC_F3_SI1_SIUFMESR0_SYNDROME_MASK) 1681 1682 #define NETC_F3_SI1_SIUFMESR0_MEM_ID_MASK (0x1F0000U) 1683 #define NETC_F3_SI1_SIUFMESR0_MEM_ID_SHIFT (16U) 1684 #define NETC_F3_SI1_SIUFMESR0_MEM_ID_WIDTH (5U) 1685 #define NETC_F3_SI1_SIUFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFMESR0_MEM_ID_SHIFT)) & NETC_F3_SI1_SIUFMESR0_MEM_ID_MASK) 1686 1687 #define NETC_F3_SI1_SIUFMESR0_M_MASK (0x40000000U) 1688 #define NETC_F3_SI1_SIUFMESR0_M_SHIFT (30U) 1689 #define NETC_F3_SI1_SIUFMESR0_M_WIDTH (1U) 1690 #define NETC_F3_SI1_SIUFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFMESR0_M_SHIFT)) & NETC_F3_SI1_SIUFMESR0_M_MASK) 1691 1692 #define NETC_F3_SI1_SIUFMESR0_MBEE_MASK (0x80000000U) 1693 #define NETC_F3_SI1_SIUFMESR0_MBEE_SHIFT (31U) 1694 #define NETC_F3_SI1_SIUFMESR0_MBEE_WIDTH (1U) 1695 #define NETC_F3_SI1_SIUFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFMESR0_MBEE_SHIFT)) & NETC_F3_SI1_SIUFMESR0_MBEE_MASK) 1696 /*! @} */ 1697 1698 /*! @name SIUFMESR1 - Station interface uncorrectable fatal memory error status register 1 */ 1699 /*! @{ */ 1700 1701 #define NETC_F3_SI1_SIUFMESR1_ADDR_MASK (0xFFFFFFFFU) 1702 #define NETC_F3_SI1_SIUFMESR1_ADDR_SHIFT (0U) 1703 #define NETC_F3_SI1_SIUFMESR1_ADDR_WIDTH (32U) 1704 #define NETC_F3_SI1_SIUFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFMESR1_ADDR_SHIFT)) & NETC_F3_SI1_SIUFMESR1_ADDR_MASK) 1705 /*! @} */ 1706 1707 /*! @name SIUNIECR - Station interface uncorrectable non-fatal integrity error configuration register */ 1708 /*! @{ */ 1709 1710 #define NETC_F3_SI1_SIUNIECR_THRESHOLD_MASK (0xFFU) 1711 #define NETC_F3_SI1_SIUNIECR_THRESHOLD_SHIFT (0U) 1712 #define NETC_F3_SI1_SIUNIECR_THRESHOLD_WIDTH (8U) 1713 #define NETC_F3_SI1_SIUNIECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNIECR_THRESHOLD_SHIFT)) & NETC_F3_SI1_SIUNIECR_THRESHOLD_MASK) 1714 1715 #define NETC_F3_SI1_SIUNIECR_RD_MASK (0x80000000U) 1716 #define NETC_F3_SI1_SIUNIECR_RD_SHIFT (31U) 1717 #define NETC_F3_SI1_SIUNIECR_RD_WIDTH (1U) 1718 #define NETC_F3_SI1_SIUNIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNIECR_RD_SHIFT)) & NETC_F3_SI1_SIUNIECR_RD_MASK) 1719 /*! @} */ 1720 1721 /*! @name SIUNIESR - Station interface uncorrectable non-fatal integrity error status register */ 1722 /*! @{ */ 1723 1724 #define NETC_F3_SI1_SIUNIESR_BLOCK_ID_MASK (0xF0U) 1725 #define NETC_F3_SI1_SIUNIESR_BLOCK_ID_SHIFT (4U) 1726 #define NETC_F3_SI1_SIUNIESR_BLOCK_ID_WIDTH (4U) 1727 #define NETC_F3_SI1_SIUNIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNIESR_BLOCK_ID_SHIFT)) & NETC_F3_SI1_SIUNIESR_BLOCK_ID_MASK) 1728 1729 #define NETC_F3_SI1_SIUNIESR_SM_ID_MASK (0x3F00U) 1730 #define NETC_F3_SI1_SIUNIESR_SM_ID_SHIFT (8U) 1731 #define NETC_F3_SI1_SIUNIESR_SM_ID_WIDTH (6U) 1732 #define NETC_F3_SI1_SIUNIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNIESR_SM_ID_SHIFT)) & NETC_F3_SI1_SIUNIESR_SM_ID_MASK) 1733 1734 #define NETC_F3_SI1_SIUNIESR_INTERR_MASK (0x80000000U) 1735 #define NETC_F3_SI1_SIUNIESR_INTERR_SHIFT (31U) 1736 #define NETC_F3_SI1_SIUNIESR_INTERR_WIDTH (1U) 1737 #define NETC_F3_SI1_SIUNIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNIESR_INTERR_SHIFT)) & NETC_F3_SI1_SIUNIESR_INTERR_MASK) 1738 /*! @} */ 1739 1740 /*! @name SIUNIECTR - Station interface uncorrectable non-fatal integrity error count register */ 1741 /*! @{ */ 1742 1743 #define NETC_F3_SI1_SIUNIECTR_COUNT_MASK (0xFFU) 1744 #define NETC_F3_SI1_SIUNIECTR_COUNT_SHIFT (0U) 1745 #define NETC_F3_SI1_SIUNIECTR_COUNT_WIDTH (8U) 1746 #define NETC_F3_SI1_SIUNIECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUNIECTR_COUNT_SHIFT)) & NETC_F3_SI1_SIUNIECTR_COUNT_MASK) 1747 /*! @} */ 1748 1749 /*! @name SIUFIECR - Station interface uncorrectable fatal integrity error configuration register */ 1750 /*! @{ */ 1751 1752 #define NETC_F3_SI1_SIUFIECR_RD_MASK (0x80000000U) 1753 #define NETC_F3_SI1_SIUFIECR_RD_SHIFT (31U) 1754 #define NETC_F3_SI1_SIUFIECR_RD_WIDTH (1U) 1755 #define NETC_F3_SI1_SIUFIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFIECR_RD_SHIFT)) & NETC_F3_SI1_SIUFIECR_RD_MASK) 1756 /*! @} */ 1757 1758 /*! @name SIUFIESR - Station interface uncorrectable fatal integrity error status register */ 1759 /*! @{ */ 1760 1761 #define NETC_F3_SI1_SIUFIESR_BLOCK_ID_MASK (0xF0U) 1762 #define NETC_F3_SI1_SIUFIESR_BLOCK_ID_SHIFT (4U) 1763 #define NETC_F3_SI1_SIUFIESR_BLOCK_ID_WIDTH (4U) 1764 #define NETC_F3_SI1_SIUFIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFIESR_BLOCK_ID_SHIFT)) & NETC_F3_SI1_SIUFIESR_BLOCK_ID_MASK) 1765 1766 #define NETC_F3_SI1_SIUFIESR_SM_ID_MASK (0x3F00U) 1767 #define NETC_F3_SI1_SIUFIESR_SM_ID_SHIFT (8U) 1768 #define NETC_F3_SI1_SIUFIESR_SM_ID_WIDTH (6U) 1769 #define NETC_F3_SI1_SIUFIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFIESR_SM_ID_SHIFT)) & NETC_F3_SI1_SIUFIESR_SM_ID_MASK) 1770 1771 #define NETC_F3_SI1_SIUFIESR_M_MASK (0x40000000U) 1772 #define NETC_F3_SI1_SIUFIESR_M_SHIFT (30U) 1773 #define NETC_F3_SI1_SIUFIESR_M_WIDTH (1U) 1774 #define NETC_F3_SI1_SIUFIESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFIESR_M_SHIFT)) & NETC_F3_SI1_SIUFIESR_M_MASK) 1775 1776 #define NETC_F3_SI1_SIUFIESR_INTERR_MASK (0x80000000U) 1777 #define NETC_F3_SI1_SIUFIESR_INTERR_SHIFT (31U) 1778 #define NETC_F3_SI1_SIUFIESR_INTERR_WIDTH (1U) 1779 #define NETC_F3_SI1_SIUFIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIUFIESR_INTERR_SHIFT)) & NETC_F3_SI1_SIUFIESR_INTERR_MASK) 1780 /*! @} */ 1781 1782 /*! @name SIMAFTCAPR - Station interface MAC address filter table capability register */ 1783 /*! @{ */ 1784 1785 #define NETC_F3_SI1_SIMAFTCAPR_NUM_MAC_AFTE_MASK (0xFFU) 1786 #define NETC_F3_SI1_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT (0U) 1787 #define NETC_F3_SI1_SIMAFTCAPR_NUM_MAC_AFTE_WIDTH (8U) 1788 #define NETC_F3_SI1_SIMAFTCAPR_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT)) & NETC_F3_SI1_SIMAFTCAPR_NUM_MAC_AFTE_MASK) 1789 /*! @} */ 1790 1791 /*! @name SIVFTCAPR - Station interface VLAN filter table capability register */ 1792 /*! @{ */ 1793 1794 #define NETC_F3_SI1_SIVFTCAPR_NUM_VLAN_FTE_MASK (0xFFU) 1795 #define NETC_F3_SI1_SIVFTCAPR_NUM_VLAN_FTE_SHIFT (0U) 1796 #define NETC_F3_SI1_SIVFTCAPR_NUM_VLAN_FTE_WIDTH (8U) 1797 #define NETC_F3_SI1_SIVFTCAPR_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIVFTCAPR_NUM_VLAN_FTE_SHIFT)) & NETC_F3_SI1_SIVFTCAPR_NUM_VLAN_FTE_MASK) 1798 /*! @} */ 1799 1800 /*! @name SIRFSCAPR - Station interface RFS capability register */ 1801 /*! @{ */ 1802 1803 #define NETC_F3_SI1_SIRFSCAPR_NUM_RFS_MASK (0x1FFU) 1804 #define NETC_F3_SI1_SIRFSCAPR_NUM_RFS_SHIFT (0U) 1805 #define NETC_F3_SI1_SIRFSCAPR_NUM_RFS_WIDTH (9U) 1806 #define NETC_F3_SI1_SIRFSCAPR_NUM_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_SIRFSCAPR_NUM_RFS_SHIFT)) & NETC_F3_SI1_SIRFSCAPR_NUM_RFS_MASK) 1807 /*! @} */ 1808 1809 /*! @name TBMR - Tx BDR 0 mode register..Tx BDR 17 mode register */ 1810 /*! @{ */ 1811 1812 #define NETC_F3_SI1_TBMR_PRIO_MASK (0x7U) 1813 #define NETC_F3_SI1_TBMR_PRIO_SHIFT (0U) 1814 #define NETC_F3_SI1_TBMR_PRIO_WIDTH (3U) 1815 #define NETC_F3_SI1_TBMR_PRIO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBMR_PRIO_SHIFT)) & NETC_F3_SI1_TBMR_PRIO_MASK) 1816 1817 #define NETC_F3_SI1_TBMR_WRR_MASK (0x70U) 1818 #define NETC_F3_SI1_TBMR_WRR_SHIFT (4U) 1819 #define NETC_F3_SI1_TBMR_WRR_WIDTH (3U) 1820 #define NETC_F3_SI1_TBMR_WRR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBMR_WRR_SHIFT)) & NETC_F3_SI1_TBMR_WRR_MASK) 1821 1822 #define NETC_F3_SI1_TBMR_CRC_MASK (0x100U) 1823 #define NETC_F3_SI1_TBMR_CRC_SHIFT (8U) 1824 #define NETC_F3_SI1_TBMR_CRC_WIDTH (1U) 1825 #define NETC_F3_SI1_TBMR_CRC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBMR_CRC_SHIFT)) & NETC_F3_SI1_TBMR_CRC_MASK) 1826 1827 #define NETC_F3_SI1_TBMR_VIH_MASK (0x200U) 1828 #define NETC_F3_SI1_TBMR_VIH_SHIFT (9U) 1829 #define NETC_F3_SI1_TBMR_VIH_WIDTH (1U) 1830 #define NETC_F3_SI1_TBMR_VIH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBMR_VIH_SHIFT)) & NETC_F3_SI1_TBMR_VIH_MASK) 1831 1832 #define NETC_F3_SI1_TBMR_EN_MASK (0x80000000U) 1833 #define NETC_F3_SI1_TBMR_EN_SHIFT (31U) 1834 #define NETC_F3_SI1_TBMR_EN_WIDTH (1U) 1835 #define NETC_F3_SI1_TBMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBMR_EN_SHIFT)) & NETC_F3_SI1_TBMR_EN_MASK) 1836 /*! @} */ 1837 1838 /*! @name TBSR - Tx BDR 0 status register..Tx BDR 17 status register */ 1839 /*! @{ */ 1840 1841 #define NETC_F3_SI1_TBSR_BUSY_MASK (0x1U) 1842 #define NETC_F3_SI1_TBSR_BUSY_SHIFT (0U) 1843 #define NETC_F3_SI1_TBSR_BUSY_WIDTH (1U) 1844 #define NETC_F3_SI1_TBSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBSR_BUSY_SHIFT)) & NETC_F3_SI1_TBSR_BUSY_MASK) 1845 1846 #define NETC_F3_SI1_TBSR_SBE_MASK (0x10000U) 1847 #define NETC_F3_SI1_TBSR_SBE_SHIFT (16U) 1848 #define NETC_F3_SI1_TBSR_SBE_WIDTH (1U) 1849 #define NETC_F3_SI1_TBSR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBSR_SBE_SHIFT)) & NETC_F3_SI1_TBSR_SBE_MASK) 1850 /*! @} */ 1851 1852 /*! @name TBBAR0 - Tx BDR 0 base address register 0..Tx BDR 17 base address register 0 */ 1853 /*! @{ */ 1854 1855 #define NETC_F3_SI1_TBBAR0_ADDRL_MASK (0xFFFFFF80U) 1856 #define NETC_F3_SI1_TBBAR0_ADDRL_SHIFT (7U) 1857 #define NETC_F3_SI1_TBBAR0_ADDRL_WIDTH (25U) 1858 #define NETC_F3_SI1_TBBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBBAR0_ADDRL_SHIFT)) & NETC_F3_SI1_TBBAR0_ADDRL_MASK) 1859 /*! @} */ 1860 1861 /*! @name TBBAR1 - Tx BDR 0 base address register 1..Tx BDR 17 base address register 1 */ 1862 /*! @{ */ 1863 1864 #define NETC_F3_SI1_TBBAR1_ADDRH_MASK (0xFFFFFFFFU) 1865 #define NETC_F3_SI1_TBBAR1_ADDRH_SHIFT (0U) 1866 #define NETC_F3_SI1_TBBAR1_ADDRH_WIDTH (32U) 1867 #define NETC_F3_SI1_TBBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBBAR1_ADDRH_SHIFT)) & NETC_F3_SI1_TBBAR1_ADDRH_MASK) 1868 /*! @} */ 1869 1870 /*! @name TBPIR - Tx BDR 0 producer index register..Tx BDR 17 producer index register */ 1871 /*! @{ */ 1872 1873 #define NETC_F3_SI1_TBPIR_BDR_INDEX_MASK (0xFFFFU) 1874 #define NETC_F3_SI1_TBPIR_BDR_INDEX_SHIFT (0U) 1875 #define NETC_F3_SI1_TBPIR_BDR_INDEX_WIDTH (16U) 1876 #define NETC_F3_SI1_TBPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBPIR_BDR_INDEX_SHIFT)) & NETC_F3_SI1_TBPIR_BDR_INDEX_MASK) 1877 /*! @} */ 1878 1879 /*! @name TBCIR - Tx BDR 0 consumer index register..Tx BDR 17 consumer index register */ 1880 /*! @{ */ 1881 1882 #define NETC_F3_SI1_TBCIR_BDR_INDEX_MASK (0xFFFFU) 1883 #define NETC_F3_SI1_TBCIR_BDR_INDEX_SHIFT (0U) 1884 #define NETC_F3_SI1_TBCIR_BDR_INDEX_WIDTH (16U) 1885 #define NETC_F3_SI1_TBCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBCIR_BDR_INDEX_SHIFT)) & NETC_F3_SI1_TBCIR_BDR_INDEX_MASK) 1886 1887 #define NETC_F3_SI1_TBCIR_STAT_ID_MASK (0xFFFF0000U) 1888 #define NETC_F3_SI1_TBCIR_STAT_ID_SHIFT (16U) 1889 #define NETC_F3_SI1_TBCIR_STAT_ID_WIDTH (16U) 1890 #define NETC_F3_SI1_TBCIR_STAT_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBCIR_STAT_ID_SHIFT)) & NETC_F3_SI1_TBCIR_STAT_ID_MASK) 1891 /*! @} */ 1892 1893 /*! @name TBLENR - Tx BDR 0 length register..Tx BDR 17 length register */ 1894 /*! @{ */ 1895 1896 #define NETC_F3_SI1_TBLENR_LENGTH_MASK (0x1FFF8U) 1897 #define NETC_F3_SI1_TBLENR_LENGTH_SHIFT (3U) 1898 #define NETC_F3_SI1_TBLENR_LENGTH_WIDTH (14U) 1899 #define NETC_F3_SI1_TBLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBLENR_LENGTH_SHIFT)) & NETC_F3_SI1_TBLENR_LENGTH_MASK) 1900 /*! @} */ 1901 1902 /*! @name TBIER - Tx BDR 0 interrupt enable register..Tx BDR 17 interrupt enable register */ 1903 /*! @{ */ 1904 1905 #define NETC_F3_SI1_TBIER_TXTIE_MASK (0x1U) 1906 #define NETC_F3_SI1_TBIER_TXTIE_SHIFT (0U) 1907 #define NETC_F3_SI1_TBIER_TXTIE_WIDTH (1U) 1908 #define NETC_F3_SI1_TBIER_TXTIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBIER_TXTIE_SHIFT)) & NETC_F3_SI1_TBIER_TXTIE_MASK) 1909 1910 #define NETC_F3_SI1_TBIER_TXFIE_MASK (0x2U) 1911 #define NETC_F3_SI1_TBIER_TXFIE_SHIFT (1U) 1912 #define NETC_F3_SI1_TBIER_TXFIE_WIDTH (1U) 1913 #define NETC_F3_SI1_TBIER_TXFIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBIER_TXFIE_SHIFT)) & NETC_F3_SI1_TBIER_TXFIE_MASK) 1914 /*! @} */ 1915 1916 /*! @name TBIDR - Tx BDR 0 interrupt detect register..Tx BDR 17 interrupt detect register */ 1917 /*! @{ */ 1918 1919 #define NETC_F3_SI1_TBIDR_TXT_MASK (0x1U) 1920 #define NETC_F3_SI1_TBIDR_TXT_SHIFT (0U) 1921 #define NETC_F3_SI1_TBIDR_TXT_WIDTH (1U) 1922 #define NETC_F3_SI1_TBIDR_TXT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBIDR_TXT_SHIFT)) & NETC_F3_SI1_TBIDR_TXT_MASK) 1923 1924 #define NETC_F3_SI1_TBIDR_TXF_MASK (0x2U) 1925 #define NETC_F3_SI1_TBIDR_TXF_SHIFT (1U) 1926 #define NETC_F3_SI1_TBIDR_TXF_WIDTH (1U) 1927 #define NETC_F3_SI1_TBIDR_TXF(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBIDR_TXF_SHIFT)) & NETC_F3_SI1_TBIDR_TXF_MASK) 1928 /*! @} */ 1929 1930 /*! @name TBICR0 - Tx BDR 0 interrupt coalescing register 0..Tx BDR 17 interrupt coalescing register 0 */ 1931 /*! @{ */ 1932 1933 #define NETC_F3_SI1_TBICR0_ICPT_MASK (0xFU) 1934 #define NETC_F3_SI1_TBICR0_ICPT_SHIFT (0U) 1935 #define NETC_F3_SI1_TBICR0_ICPT_WIDTH (4U) 1936 #define NETC_F3_SI1_TBICR0_ICPT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBICR0_ICPT_SHIFT)) & NETC_F3_SI1_TBICR0_ICPT_MASK) 1937 1938 #define NETC_F3_SI1_TBICR0_ICEN_MASK (0x80000000U) 1939 #define NETC_F3_SI1_TBICR0_ICEN_SHIFT (31U) 1940 #define NETC_F3_SI1_TBICR0_ICEN_WIDTH (1U) 1941 #define NETC_F3_SI1_TBICR0_ICEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBICR0_ICEN_SHIFT)) & NETC_F3_SI1_TBICR0_ICEN_MASK) 1942 /*! @} */ 1943 1944 /*! @name TBICR1 - Tx BDR 0 interrupt coalescing register 1..Tx BDR 17 interrupt coalescing register 1 */ 1945 /*! @{ */ 1946 1947 #define NETC_F3_SI1_TBICR1_ICTT_MASK (0xFFFFFFFFU) 1948 #define NETC_F3_SI1_TBICR1_ICTT_SHIFT (0U) 1949 #define NETC_F3_SI1_TBICR1_ICTT_WIDTH (32U) 1950 #define NETC_F3_SI1_TBICR1_ICTT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_TBICR1_ICTT_SHIFT)) & NETC_F3_SI1_TBICR1_ICTT_MASK) 1951 /*! @} */ 1952 1953 /*! @name RBMR - Rx BDR 0 mode register..Rx BDR 17 mode register */ 1954 /*! @{ */ 1955 1956 #define NETC_F3_SI1_RBMR_AL_MASK (0x1U) 1957 #define NETC_F3_SI1_RBMR_AL_SHIFT (0U) 1958 #define NETC_F3_SI1_RBMR_AL_WIDTH (1U) 1959 #define NETC_F3_SI1_RBMR_AL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBMR_AL_SHIFT)) & NETC_F3_SI1_RBMR_AL_MASK) 1960 1961 #define NETC_F3_SI1_RBMR_BDS_MASK (0x4U) 1962 #define NETC_F3_SI1_RBMR_BDS_SHIFT (2U) 1963 #define NETC_F3_SI1_RBMR_BDS_WIDTH (1U) 1964 #define NETC_F3_SI1_RBMR_BDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBMR_BDS_SHIFT)) & NETC_F3_SI1_RBMR_BDS_MASK) 1965 1966 #define NETC_F3_SI1_RBMR_CM_MASK (0x10U) 1967 #define NETC_F3_SI1_RBMR_CM_SHIFT (4U) 1968 #define NETC_F3_SI1_RBMR_CM_WIDTH (1U) 1969 #define NETC_F3_SI1_RBMR_CM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBMR_CM_SHIFT)) & NETC_F3_SI1_RBMR_CM_MASK) 1970 1971 #define NETC_F3_SI1_RBMR_VTE_MASK (0x20U) 1972 #define NETC_F3_SI1_RBMR_VTE_SHIFT (5U) 1973 #define NETC_F3_SI1_RBMR_VTE_WIDTH (1U) 1974 #define NETC_F3_SI1_RBMR_VTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBMR_VTE_SHIFT)) & NETC_F3_SI1_RBMR_VTE_MASK) 1975 1976 #define NETC_F3_SI1_RBMR_VTPD_MASK (0x40U) 1977 #define NETC_F3_SI1_RBMR_VTPD_SHIFT (6U) 1978 #define NETC_F3_SI1_RBMR_VTPD_WIDTH (1U) 1979 #define NETC_F3_SI1_RBMR_VTPD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBMR_VTPD_SHIFT)) & NETC_F3_SI1_RBMR_VTPD_MASK) 1980 1981 #define NETC_F3_SI1_RBMR_CRC_MASK (0x100U) 1982 #define NETC_F3_SI1_RBMR_CRC_SHIFT (8U) 1983 #define NETC_F3_SI1_RBMR_CRC_WIDTH (1U) 1984 #define NETC_F3_SI1_RBMR_CRC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBMR_CRC_SHIFT)) & NETC_F3_SI1_RBMR_CRC_MASK) 1985 1986 #define NETC_F3_SI1_RBMR_EN_MASK (0x80000000U) 1987 #define NETC_F3_SI1_RBMR_EN_SHIFT (31U) 1988 #define NETC_F3_SI1_RBMR_EN_WIDTH (1U) 1989 #define NETC_F3_SI1_RBMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBMR_EN_SHIFT)) & NETC_F3_SI1_RBMR_EN_MASK) 1990 /*! @} */ 1991 1992 /*! @name RBSR - Rx BDR 0 status register..Rx BDR 17 status register */ 1993 /*! @{ */ 1994 1995 #define NETC_F3_SI1_RBSR_EMPTY_MASK (0x1U) 1996 #define NETC_F3_SI1_RBSR_EMPTY_SHIFT (0U) 1997 #define NETC_F3_SI1_RBSR_EMPTY_WIDTH (1U) 1998 #define NETC_F3_SI1_RBSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBSR_EMPTY_SHIFT)) & NETC_F3_SI1_RBSR_EMPTY_MASK) 1999 2000 #define NETC_F3_SI1_RBSR_SBE_MASK (0x10000U) 2001 #define NETC_F3_SI1_RBSR_SBE_SHIFT (16U) 2002 #define NETC_F3_SI1_RBSR_SBE_WIDTH (1U) 2003 #define NETC_F3_SI1_RBSR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBSR_SBE_SHIFT)) & NETC_F3_SI1_RBSR_SBE_MASK) 2004 /*! @} */ 2005 2006 /*! @name RBBSR - Rx BDR 0 buffer size register..Rx BDR 17 buffer size register */ 2007 /*! @{ */ 2008 2009 #define NETC_F3_SI1_RBBSR_BSIZE_MASK (0xFFFFU) 2010 #define NETC_F3_SI1_RBBSR_BSIZE_SHIFT (0U) 2011 #define NETC_F3_SI1_RBBSR_BSIZE_WIDTH (16U) 2012 #define NETC_F3_SI1_RBBSR_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBBSR_BSIZE_SHIFT)) & NETC_F3_SI1_RBBSR_BSIZE_MASK) 2013 /*! @} */ 2014 2015 /*! @name RBCIR - Rx BDR 0 consumer index register..Rx BDR 17 consumer index register */ 2016 /*! @{ */ 2017 2018 #define NETC_F3_SI1_RBCIR_BDR_INDEX_MASK (0xFFFFU) 2019 #define NETC_F3_SI1_RBCIR_BDR_INDEX_SHIFT (0U) 2020 #define NETC_F3_SI1_RBCIR_BDR_INDEX_WIDTH (16U) 2021 #define NETC_F3_SI1_RBCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBCIR_BDR_INDEX_SHIFT)) & NETC_F3_SI1_RBCIR_BDR_INDEX_MASK) 2022 /*! @} */ 2023 2024 /*! @name RBBAR0 - Rx BDR 0 base address register 0..Rx BDR 17 base address register 0 */ 2025 /*! @{ */ 2026 2027 #define NETC_F3_SI1_RBBAR0_ADDRL_MASK (0xFFFFFF80U) 2028 #define NETC_F3_SI1_RBBAR0_ADDRL_SHIFT (7U) 2029 #define NETC_F3_SI1_RBBAR0_ADDRL_WIDTH (25U) 2030 #define NETC_F3_SI1_RBBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBBAR0_ADDRL_SHIFT)) & NETC_F3_SI1_RBBAR0_ADDRL_MASK) 2031 /*! @} */ 2032 2033 /*! @name RBBAR1 - Rx BDR 0 base address register 1..Rx BDR 17 base address register 1 */ 2034 /*! @{ */ 2035 2036 #define NETC_F3_SI1_RBBAR1_ADDRH_MASK (0xFFFFFFFFU) 2037 #define NETC_F3_SI1_RBBAR1_ADDRH_SHIFT (0U) 2038 #define NETC_F3_SI1_RBBAR1_ADDRH_WIDTH (32U) 2039 #define NETC_F3_SI1_RBBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBBAR1_ADDRH_SHIFT)) & NETC_F3_SI1_RBBAR1_ADDRH_MASK) 2040 /*! @} */ 2041 2042 /*! @name RBPIR - Rx BDR 0 producer index register..Rx BDR 17 producer index register */ 2043 /*! @{ */ 2044 2045 #define NETC_F3_SI1_RBPIR_BDR_INDEX_MASK (0xFFFFU) 2046 #define NETC_F3_SI1_RBPIR_BDR_INDEX_SHIFT (0U) 2047 #define NETC_F3_SI1_RBPIR_BDR_INDEX_WIDTH (16U) 2048 #define NETC_F3_SI1_RBPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBPIR_BDR_INDEX_SHIFT)) & NETC_F3_SI1_RBPIR_BDR_INDEX_MASK) 2049 /*! @} */ 2050 2051 /*! @name RBLENR - Rx BDR 0 length register..Rx BDR 17 length register */ 2052 /*! @{ */ 2053 2054 #define NETC_F3_SI1_RBLENR_LENGTH_MASK (0x1FFF8U) 2055 #define NETC_F3_SI1_RBLENR_LENGTH_SHIFT (3U) 2056 #define NETC_F3_SI1_RBLENR_LENGTH_WIDTH (14U) 2057 #define NETC_F3_SI1_RBLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBLENR_LENGTH_SHIFT)) & NETC_F3_SI1_RBLENR_LENGTH_MASK) 2058 /*! @} */ 2059 2060 /*! @name RBDCR - Rx BDR 0 drop count register..Rx BDR 17 drop count register */ 2061 /*! @{ */ 2062 2063 #define NETC_F3_SI1_RBDCR_COUNT_MASK (0xFFFFFFFFU) 2064 #define NETC_F3_SI1_RBDCR_COUNT_SHIFT (0U) 2065 #define NETC_F3_SI1_RBDCR_COUNT_WIDTH (32U) 2066 #define NETC_F3_SI1_RBDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBDCR_COUNT_SHIFT)) & NETC_F3_SI1_RBDCR_COUNT_MASK) 2067 /*! @} */ 2068 2069 /*! @name RBIER - Rx BDR 0 interrupt enable register..Rx BDR 17 interrupt enable register */ 2070 /*! @{ */ 2071 2072 #define NETC_F3_SI1_RBIER_RXTIE_MASK (0x1U) 2073 #define NETC_F3_SI1_RBIER_RXTIE_SHIFT (0U) 2074 #define NETC_F3_SI1_RBIER_RXTIE_WIDTH (1U) 2075 #define NETC_F3_SI1_RBIER_RXTIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBIER_RXTIE_SHIFT)) & NETC_F3_SI1_RBIER_RXTIE_MASK) 2076 /*! @} */ 2077 2078 /*! @name RBIDR - Rx BDR 0 interrupt detect register..Rx BDR 17 interrupt detect register */ 2079 /*! @{ */ 2080 2081 #define NETC_F3_SI1_RBIDR_RXT_MASK (0x1U) 2082 #define NETC_F3_SI1_RBIDR_RXT_SHIFT (0U) 2083 #define NETC_F3_SI1_RBIDR_RXT_WIDTH (1U) 2084 #define NETC_F3_SI1_RBIDR_RXT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBIDR_RXT_SHIFT)) & NETC_F3_SI1_RBIDR_RXT_MASK) 2085 /*! @} */ 2086 2087 /*! @name RBICR0 - Rx BDR 0 interrupt coalescing register 0..Rx BDR 17 interrupt coalescing register 0 */ 2088 /*! @{ */ 2089 2090 #define NETC_F3_SI1_RBICR0_ICPT_MASK (0x1FFU) 2091 #define NETC_F3_SI1_RBICR0_ICPT_SHIFT (0U) 2092 #define NETC_F3_SI1_RBICR0_ICPT_WIDTH (9U) 2093 #define NETC_F3_SI1_RBICR0_ICPT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBICR0_ICPT_SHIFT)) & NETC_F3_SI1_RBICR0_ICPT_MASK) 2094 2095 #define NETC_F3_SI1_RBICR0_ICEN_MASK (0x80000000U) 2096 #define NETC_F3_SI1_RBICR0_ICEN_SHIFT (31U) 2097 #define NETC_F3_SI1_RBICR0_ICEN_WIDTH (1U) 2098 #define NETC_F3_SI1_RBICR0_ICEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBICR0_ICEN_SHIFT)) & NETC_F3_SI1_RBICR0_ICEN_MASK) 2099 /*! @} */ 2100 2101 /*! @name RBICR1 - Rx BDR 0 interrupt coalescing register 1..Rx BDR 17 interrupt coalescing register 1 */ 2102 /*! @{ */ 2103 2104 #define NETC_F3_SI1_RBICR1_ICTT_MASK (0xFFFFFFFFU) 2105 #define NETC_F3_SI1_RBICR1_ICTT_SHIFT (0U) 2106 #define NETC_F3_SI1_RBICR1_ICTT_WIDTH (32U) 2107 #define NETC_F3_SI1_RBICR1_ICTT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI1_RBICR1_ICTT_SHIFT)) & NETC_F3_SI1_RBICR1_ICTT_MASK) 2108 /*! @} */ 2109 2110 /*! 2111 * @} 2112 */ /* end of group NETC_F3_SI1_Register_Masks */ 2113 2114 /*! 2115 * @} 2116 */ /* end of group NETC_F3_SI1_Peripheral_Access_Layer */ 2117 2118 #endif /* #if !defined(S32Z2_NETC_F3_SI1_H_) */ 2119
