Searched refs:NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT (Results 1 – 3 of 3) sorted by relevance
372 …C0_BASE->PSIPMMR |= ((uint32)((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT))); in Netc_Eth_Ip_VsiToPsi_Enable_Multicast()394 …_BASE->PSIPMMR &= ~((uint32) ((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT))); in Netc_Eth_Ip_VsiToPsi_Disable_Multicast()413 …0_BASE->PSIPMMR &= ~((uint32)((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT))); in Netc_Eth_Ip_VsiToPsi_Close_Filter()543 …_INDEX]->generalConfig->maskMACPromiscuousMulticastEnable) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT) | \ in Netc_Eth_Ip_InitVSIAfterFlr()
1372 …*config->generalConfig).maskMACPromiscuousMulticastEnable) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT) | \ in Netc_Eth_Ip_InitSI()7805 … IP_NETC__ENETC0_BASE->PSIPMMR |= ((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));7812 … IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));7852 … IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)1U << (CtrlIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT));
576 #define NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT (16U) macro578 …MR_SI0_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)) & N…
