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Searched refs:NETC_F3_PSICFGR0_VTE_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_NETC_F3.h983 #define NETC_F3_PSICFGR0_VTE_MASK (0x1000U) macro
986 … (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_VTE_SHIFT)) & NETC_F3_PSICFGR0_VTE_MASK)
/hal_nxp-latest/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip_Irq.c600 …SICFGR0 &= ~(NETC_F3_PSICFGR0_SIVC_MASK | NETC_F3_PSICFGR0_SIVIE_MASK | NETC_F3_PSICFGR0_VTE_MASK); in Netc_Eth_Ip_InitVSIAfterFlr()
DNetc_Eth_Ip.c7230 …SICFGR0 &= ~(NETC_F3_PSICFGR0_SIVC_MASK | NETC_F3_PSICFGR0_SIVIE_MASK | NETC_F3_PSICFGR0_VTE_MASK);