1 /* 2 * Copyright 2022-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NETC_ETHSWT_IP_CFG_DEFINES_H 8 #define NETC_ETHSWT_IP_CFG_DEFINES_H 9 10 /** 11 * @file Netc_EthSwt_Ip_Cfg_Defines.h 12 * @addtogroup NETC_ETHSWT_IP NETC_ETHSWT Driver 13 * @{ 14 */ 15 16 #ifdef __cplusplus 17 extern "C"{ 18 #endif 19 20 /*================================================================================================== 21 * INCLUDE FILES 22 * 1) system and project includes 23 * 2) needed interfaces from external units 24 * 3) internal and external interfaces from this unit 25 ==================================================================================================*/ 26 #include "Mcal.h" 27 #include "S32Z2_NETC_F3_COMMON.h" 28 #include "S32Z2_ENETC_PORT.h" 29 #include "S32Z2_NETC_F3_SI0.h" 30 #include "S32Z2_NETC_F3.h" 31 #include "S32Z2_NETC_F0_PCI_HDR_TYPE0.h" 32 #include "S32Z2_NETC_F1_PCI_HDR_TYPE0.h" 33 #include "S32Z2_NETC_F2_PCI_HDR_TYPE0.h" 34 #include "S32Z2_NETC_F3_PCI_HDR_TYPE0.h" 35 #include "S32Z2_ENETC_PORT.h" 36 #include "S32Z2_SW_PORT0.h" 37 #include "S32Z2_SW_PORT1.h" 38 #include "S32Z2_SW_PORT2.h" 39 #include "S32Z2_SW_ETH_MAC_PORT0.h" 40 #include "S32Z2_SW_ETH_MAC_PORT1.h" 41 #include "S32Z2_SW_PSEUDO_MAC_PORT2.h" 42 #include "S32Z2_NETC_IERB.h" 43 #include "S32Z2_NETC_F2.h" 44 #include "S32Z2_NETC_F2_GLOBAL.h" 45 #include "S32Z2_NETC_F2_COMMON.h" 46 #include "S32Z2_NETC_PRIV.h" 47 #include "S32Z2_NETC_F1.h" 48 #include "S32Z2_GPR1.h" 49 #include "S32Z2_TMR0_BASE.h" 50 51 /*================================================================================================== 52 * SOURCE FILE VERSION INFORMATION 53 ==================================================================================================*/ 54 #define NETC_ETHSWT_IP_CFG_DEFINES_VENDOR_ID 43 55 #define NETC_ETHSWT_IP_CFG_DEFINES_MODULE_ID 89 56 #define NETC_ETHSWT_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 57 #define NETC_ETHSWT_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 58 #define NETC_ETHSWT_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 59 #define NETC_ETHSWT_IP_CFG_DEFINES_SW_MAJOR_VERSION 2 60 #define NETC_ETHSWT_IP_CFG_DEFINES_SW_MINOR_VERSION 0 61 #define NETC_ETHSWT_IP_CFG_DEFINES_SW_PATCH_VERSION 0 62 63 /*================================================================================================== 64 * FILE VERSION CHECKS 65 ==================================================================================================*/ 66 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 67 /* Check if current file and Mcal.h header file are of the same Autosar version */ 68 #if ((NETC_ETHSWT_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ 69 (NETC_ETHSWT_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) 70 #error "AUTOSAR Version Numbers of Netc_EthSwt_Ip_Cfg_Defines.h and Mcal.h are different" 71 #endif 72 #endif 73 74 /*================================================================================================== 75 * CONSTANTS 76 ==================================================================================================*/ 77 78 /*================================================================================================== 79 * DEFINES AND MACROS 80 ==================================================================================================*/ 81 82 #define NETC_NUMBER_OF_PRIORITIES (8U) /*!< Number of priorities.*/ 83 84 #define NETC_TXBD_BUF_LEN_MASK (0x0000FFFFUL) /*!< TX buffer length mask.*/ 85 #define NETC_TXBD_FINAL_MASK (0x80000000UL) /*!< TX final mask.*/ 86 #define NETC_TXBD_EXTENDED_BUFFER_MASK (0x40000000UL) /*!< TX extended buffer mask.*/ 87 #define NETC_TXBD_WRITTEN_MASK (0x08000000UL) /*!< TX written mask.*/ 88 89 #define NETC_RXBD_FINAL_MASK (0x80000000UL) /*!< RX final mask.*/ 90 91 #define Netc_EthSwt_Ip_PortBaseType SW_ETH_MAC_PORT0_Type /*!< Port base type.*/ 92 #define Netc_EthSwt_Ip_PseudoPortBaseType SW_PSEUDO_MAC_PORT2_Type /*!< Pseudo base type.*/ 93 94 #define FEATURE_NETC_ETHSWT_IP_NUMBER_OF_SWTS (1U) /*!< Number of switchs.*/ 95 96 #define NETC_ETHSWT_IP_FDBTABLE_REQBUFFER_LEN (48U) /*!< the length of request data buffer in bytes for FDB and other small tables */ 97 #define NETC_ETHSWT_IP_EGRESSTREAMENTTABLE_RESBUFFER_LEN (20U) /*!< 20 bytes is response buffer lenth*/ 98 #define NETC_ETHSWT_IP_FDBTABLE_QUERY_REQBUFFER_LEN (36U) /*!< 36 bytes is request buffer lenth for query and delete cmd of FDB table*/ 99 #define NETC_ETHSWT_IP_FDBTABLE_RESBUFFER_LEN (36U) /*!< 36 bytes is response buffer lenth*/ 100 #define NETC_ETHSWT_IP_VLANFILTERTABLE_REQBUFFER_LEN (24U) /*!< the length of request data buffer in bytes for vlan filter table */ 101 #define NETC_ETHSWT_IP_VLANFILTERTABLE_RESBUFFER_LEN (28U) /*!< 28 bytes is response buffer lenth*/ 102 103 #define NETC_ETHSWT_IP_RATEPOLICERTABLE_REQBUFFER_LEN (27U) /*!< the length of request data buffer in bytes for add cmd for rate policer table */ 104 #define NETC_ETHSWT_IP_RATEPOLICERTABLE_RSPBUFFER_LEN (108U) /*!< the length of response data buffer in bytes for rate policer table */ 105 106 #define NETC_ETHSWT_IP_EGRESSCOUNTTABLE_RSPBUFFER_LEN (20U) /*!< the length of response data buffer in bytes for Egress Count table */ 107 108 #define NETC_ETHSWT_IP_INGRESSPORTFILTERTABLE_REQBUFFER_LEN (224U) /*!< the length of request data buffer in bytes for Ingress Port Filter table */ 109 #define NETC_ETHSWT_IP_INGRESSPORTFILTERTABLE_RSPBUFFER_LEN (236U) /*!< the length of response data buffer in bytes for Ingress Port Filter table */ 110 111 #define NETC_ETHSWT_IP_INGRESSSTREAMTABLE_REQBUFFER_LEN (46U) /*!< the length of request data buffer in bytes for add and update cmd for ingress stream table */ 112 #define NETC_ETHSWT_IP_INGRESSSTREAMTABLE_RSPBUFFER_LEN (42U) /*!< the length of response data buffer in bytes for ingress stream table */ 113 114 #define NETC_ETHSWT_IP_ISFILTERTABLE_REQBUFFER_LEN (28U) /*!< the length of request data buffer in bytes for add and update cmd for ingress stream filter table */ 115 #define NETC_ETHSWT_IP_ISFILTERTABLE_OTHER_REQBUFFER_LEN (12U) /*!< the length of request data buffer in bytes for query (search) and delete cmd for ingress stream filter table */ 116 #define NETC_ETHSWT_IP_ISFILTERTABLE_RSPBUFFER_LEN (32U) /*!< the length of response data buffer in bytes for ingress stream filter table */ 117 118 #define NETC_ETHSWT_IP_SGITABLE_REQBUFFER_LEN (26U) /*!< the length of request data buffer in bytes for add and update cmd for stream gate instance table */ 119 #define NETC_ETHSWT_IP_SGITABLE_RSPBUFFER_LEN (48U) /*!< the length of response data buffer in bytes for stream gate instance table */ 120 121 #define NETC_ETHSWT_IP_TABLE_COMMON_REQBUFFER_8BYTE_LEN (8U) /*!< 8 bytes request data buffer length for query and delete cmd for tables */ 122 #define NETC_ETHSWT_IP_TABLE_COMMON_RSPBUFFER_0BYTE_LEN (0U) /*!< 0 bytes response data buffer length for add, update and delete cmd for tables */ 123 #define NETC_ETHSWT_IP_TABLE_COMMON_RSPBUFFER_4BYTE_LEN (4U) /*!< 4 bytes response data buffer length for add, update and delete cmd for tables */ 124 125 #define NETC_ETHSWT_IP_TGSTABLE_RSPBUFFER_LEN (12U) /*!< the length of response data buffer in bytes for time gate scheduling table */ 126 #define NETC_ETHSWT_IP_FRMTABLE_REQBUFFER_LEN (32U) /*!< the length of request data buffer in bytes for frame modification table */ 127 #define NETC_ETHSWT_IP_FRMTABLE_RSPBUFFER_LEN (28U) /*!< the length of response data buffer in bytes for frame modification table */ 128 #define NETC_ETHSWT_IP_ETMTABLE_REQBUFFER_LEN (24U) /*!< the length of request data buffer in bytes for egress treatment table */ 129 130 #define NETC_ETHSWT_IP_ISQGTABLE_REQBUFFER_LEN (9U) /*!< the length of request data buffer in bytes for add and update cmd for ingress sequence generation table */ 131 #define NETC_ETHSWT_IP_ISQGTABLE_RSPBUFFER_LEN (8U) /*!< the length of response data buffer in bytes for query cmd for ingress sequence generation table */ 132 133 #define NETC_ETHSWT_IP_EGRSQRTABLE_REQBUFFER_LEN (16U) /*!< the length of request data buffer in bytes for update and query cmd for Egress sequence recovery table */ 134 #define NETC_ETHSWT_IP_EGRSQRTABLE_RSPBUFFER_LEN (84U) /*!< the length of response data buffer in bytes for query cmd for Egress sequence recovery table */ 135 #define NETC_ETHSWT_IP_ISITABLE_ADD_REQBUFFER_LEN (28U) /*!< the length of request data buffer in bytes for add and update cmd for ingress stream identification table */ 136 #define NETC_ETHSWT_IP_ISITABLE_QUERY_REQBUFFER_LEN (24U) /*!< the length of request data buffer in bytes for query and delete cmd for ingress stream identification table */ 137 #define NETC_ETHSWT_IP_ISITABLE_RSQBUFFER_LEN (32U) /*!< the length of response data buffer in bytes for query cmd for ingress stream identification table */ 138 139 #define NETC_ETHSWT_IP_EGRSCHTABLE_REQBUFFER_LEN (20U) /*!< the length of request data buffer in bytes for update cmd for Egress scheduler table */ 140 #define NETC_ETHSWT_IP_EGRSCHTABLE_RSPBUFFER_LEN (16U) /*!< the length of response data buffer in bytes for query cmd for Egress scheduler table */ 141 142 #define NETC_ETHSWT_IP_ISCTABLE_RSPBUFFER_LEN (36U) /*!< the lenght of response data buffer in bytes for query cmd for ingress stream count table */ 143 144 /* The maximum number of Weighted Fair Share Queues */ 145 #define NETC_ETHSWT_WBFS_QUEUES_NB (8U) 146 147 #define NETC_ETHSWT_IP_HOSTREASON_REGULAR_FRAME (0x00000000UL) 148 #define NETC_ETHSWT_IP_HOSTREASON_INGR_MIRROR (0x00000001UL) 149 #define NETC_ETHSWT_IP_HOSTREASON_MAC_LEARN (0x00000002UL) 150 #define NETC_ETHSWT_IP_HOSTREASON_TIMESTAMP (0x00000003UL) 151 #define NETC_ETHSWT_IP_HOSTREASON_RESERVEDx4 (0x00000004UL) 152 #define NETC_ETHSWT_IP_HOSTREASON_RESERVEDx5 (0x00000005UL) 153 #define NETC_ETHSWT_IP_HOSTREASON_RESERVEDx6 (0x00000006UL) 154 #define NETC_ETHSWT_IP_HOSTREASON_RESERVEDx7 (0x00000007UL) 155 #define NETC_ETHSWT_IP_HOSTREASON_SW_PTP (0x00000008UL) 156 #define NETC_ETHSWT_IP_HOSTREASON_SWx9 (0x00000009UL) 157 #define NETC_ETHSWT_IP_HOSTREASON_SWxA (0x0000000AUL) 158 #define NETC_ETHSWT_IP_HOSTREASON_SWxB (0x0000000BUL) 159 #define NETC_ETHSWT_IP_HOSTREASON_SWxC (0x0000000CUL) 160 #define NETC_ETHSWT_IP_HOSTREASON_SWxD (0x0000000DUL) 161 #define NETC_ETHSWT_IP_HOSTREASON_SWxE (0x0000000EUL) 162 #define NETC_ETHSWT_IP_HOSTREASON_SWxF (0x0000000FUL) 163 164 /* The maximum number of gate control list */ 165 #define NETC_ETHSWT_MAX_NUMBER_OF_GATECONTROLLIST_ENTRIES (8U) 166 167 /* NETC dev error detected. */ 168 #define NETC_ETHSWT_IP_DEV_ERROR_DETECT (STD_OFF) 169 170 /*!< The length of response data buffer in bytes for time gate scheduling table. */ 171 #define NETC_ETHSWT_IP_TGSTABLE_ADD_REQBUFFER_LEN (92U) 172 #define NETC_ETHSWT_IP_TABLEDATA_BUFFER_LENGTH (59U) 173 #define NETC_ETHSWT_IP_CONFIG_LINK_PROTOCOL (STD_ON) 174 175 /** @brief Define used to enable/disable timer syncronization. */ 176 #define NETC_ETHSWT_TIMER_SYNC_MASK (0x1U) 177 178 /*================================================================================================== 179 * ENUMS 180 ==================================================================================================*/ 181 182 /*! 183 * @brief Netc_EthSwt counter enum Netc_EthSwt_Ip_SingleCounterType 184 * @implements Netc_EthSwt_Ip_SingleCounterType_enum 185 */ 186 typedef enum { 187 NETC_ETHSWT_IP_RX_ETH_OCTETS_COUNT = 0x100U, /*!< Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn) (PM0_REOCTn) */ 188 NETC_ETHSWT_IP_RX_OCTETS_COUNT = 0x108U, /*!< Supported by pseudo port. Port MAC 0 Receive Octets Counter(iflnOctetsn) (PM0_ROCTn) */ 189 NETC_ETHSWT_IP_RX_ALIGN_ERR_COUNT = 0x110U, /*!< Port MAC 0 Receive Alignment Error Counter Register(aAlignmentErrorsn) (PM0_RALNn)) */ 190 NETC_ETHSWT_IP_RX_VALID_PAUSE_FRM_COUNT = 0x118U, /*!< Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) (PM0_RXPFn) */ 191 NETC_ETHSWT_IP_RX_FRM_COUNT = 0x120U, /*!< Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn) (PM0_RFRMn) */ 192 NETC_ETHSWT_IP_RX_FRM_CHK_SEQUENCE_COUNT = 0x128U, /*!< Port MAC 0 Receive Frame Check Sequence Error Counter Register() (PM0_RFCSn) */ 193 NETC_ETHSWT_IP_RX_VLAN_FRM_COUNT = 0x130U, /*!< Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn) (PM0_RVLANn) */ 194 NETC_ETHSWT_IP_RX_FRM_ERROR_COUNT = 0x138U, /*!< Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn) (PM0_RERRn) */ 195 NETC_ETHSWT_IP_RX_UNICAST_FRM_COUNT = 0x140U, /*!< Supported by pseudo port. Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn) (PM0_RUCAn) */ 196 NETC_ETHSWT_IP_RX_MULTICAST_FRM_COUNT = 0x148U, /*!< Supported by pseudo port. Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn) (PM0_RMCAn) */ 197 NETC_ETHSWT_IP_RX_BROADCAST_FRM_COUNT = 0x150U, /*!< Supported by pseudo port. Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) (PM0_RBCAn) */ 198 NETC_ETHSWT_IP_RX_DROPPED_PKTS_COUNT = 0x158U, /*!< Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn) (PM0_RDRPn) */ 199 NETC_ETHSWT_IP_RX_PKTS_COUNT = 0x160U, /*!< Port MAC 0 Receive Packets Counter Register(etherStatsPktsn) (PM0_RPKTn) */ 200 NETC_ETHSWT_IP_RX_UNDERSIZED_PKT_COUNT = 0x168U, /*!< Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) (PM0_RUNDn) */ 201 NETC_ETHSWT_IP_RX_64_OCTETS_PKT_COUNT = 0x170U, /*!< Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) (PM0_R64n) */ 202 NETC_ETHSWT_IP_RX_127_OCTETS_PKT_COUNT = 0x178U, /*!< Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) (PM0_R127n) */ 203 NETC_ETHSWT_IP_RX_255_OCTETS_PKT_COUNT = 0x180U, /*!< Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) (PM0_R255n) */ 204 NETC_ETHSWT_IP_RX_511_OCTETS_PKT_COUNT = 0x188U, /*!< Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) (PM0_R511n) */ 205 NETC_ETHSWT_IP_RX_1023_OCTETS_PKT_COUNT = 0x190U, /*!< Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) (PM0_R1023n) */ 206 NETC_ETHSWT_IP_RX_1522_OCTETS_PKT_COUNT = 0x198U, /*!< Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) (PM0_R1522n) */ 207 NETC_ETHSWT_IP_RX_1523_TOMAXOCTETS_PKT_COUNT = 0x1A0U, /*!< Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) (PM0_R1523Xn) */ 208 NETC_ETHSWT_IP_RX_OVERSIZED_PKT_COUNT = 0x1A8U, /*!< Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) (PM0_ROVRn) */ 209 NETC_ETHSWT_IP_RX_JABBER_PKT_COUNT = 0x1B0U, /*!< Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn) (PM0_RJBRn) */ 210 NETC_ETHSWT_IP_RX_FRAGMENT_PKT_COUNT = 0x1B8U, /*!< Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn (PM0_RFRGn) */ 211 NETC_ETHSWT_IP_RX_CONTROL_PKT_COUNT = 0x1C0U, /*!< Port MAC 0 Receive Control Packet Counter Register (PM0_RCNPn) */ 212 NETC_ETHSWT_IP_RX_DROPPED_NOT_TRUNCATED_PKT_COUNT = 0x1C8U, /*!< Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) (PM0_RDRNTPn) */ 213 NETC_ETHSWT_IP_RX_VALID_SMALL_PKT_COUNTER = 0x5D0U, /*!< Port MAC 0 Receive Valid Small Packet Counter Register (PM0_RMIN63n) */ 214 215 NETC_ETHSWT_IP_TX_ETH_OCTETS_COUNT = 0x200U, /*!< Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn) (PM0_TEOCTn) */ 216 NETC_ETHSWT_IP_TX_OCTETS_COUNT = 0x208U, /*!< Supported by pseudo port. Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn) (PM0_TOCTn) */ 217 NETC_ETHSWT_IP_TX_EXCESS_DEFER_ERR_COUNT = 0x210U, /*!< Port MAC 0 Excess Defer Error Counter Register(aFramesWithExccessiveDeferral) (PM0_TEDFRn)) */ 218 NETC_ETHSWT_IP_TX_VALID_PAUSE_FRM_COUNT = 0x218U, /*!< Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) (PM0_TXPFn) */ 219 NETC_ETHSWT_IP_TX_FRM_COUNT = 0x220U, /*!< Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn) (PM0_TFRMn) */ 220 NETC_ETHSWT_IP_TX_FRM_CHK_SEQUENCE_COUNT = 0x228U, /*!< Port MAC 0 Transmit Frame Check Sequence Error Counter Register() (PM0_TFCSn) */ 221 NETC_ETHSWT_IP_TX_VLAN_FRM_COUNT = 0x230U, /*!< Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) (PM0_TVLANn) */ 222 NETC_ETHSWT_IP_TX_FRM_ERROR_COUNT = 0x238U, /*!< Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn) (PM0_TERRn) */ 223 NETC_ETHSWT_IP_TX_UNICAST_FRM_COUNT = 0x240U, /*!< Supported by pseudo port. Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) (PM0_TUCAn) */ 224 NETC_ETHSWT_IP_TX_MULTICAST_FRM_COUNT = 0x248U, /*!< Supported by pseudo port. Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) (PM0_TMCAn) */ 225 NETC_ETHSWT_IP_TX_BROADCAST_FRM_COUNT = 0x250U, /*!< Supported by pseudo port. Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) (PM0_TBCAn) */ 226 NETC_ETHSWT_IP_TX_PKTS_COUNT = 0x260U, /*!< Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn) (PM0_TPKTn) */ 227 NETC_ETHSWT_IP_TX_UNDERSIZED_PKT_COUNT = 0x268U, /*!< Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) (PM0_TUNDn) */ 228 NETC_ETHSWT_IP_TX_64_OCTETS_PKT_COUNT = 0x270U, /*!< Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) (PM0_T64n) */ 229 NETC_ETHSWT_IP_TX_127_OCTETS_PKT_COUNT = 0x278U, /*!< Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) (PM0_T127n) */ 230 NETC_ETHSWT_IP_TX_255_OCTETS_PKT_COUNT = 0x280U, /*!< Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) (PM0_T255n) */ 231 NETC_ETHSWT_IP_TX_511_OCTETS_PKT_COUNT = 0x288U, /*!< Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) (PM0_T511n) */ 232 NETC_ETHSWT_IP_TX_1023_OCTETS_PKT_COUNT = 0x290U, /*!< Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) (PM0_T1023n) */ 233 NETC_ETHSWT_IP_TX_1522_OCTETS_PKT_COUNT = 0x298U, /*!< Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) (PM0_T1522n) */ 234 NETC_ETHSWT_IP_TX_1523_TOMAXOCTETS_PKT_COUNT = 0x2A0U, /*!< Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) (PM0_T1523Xn) */ 235 NETC_ETHSWT_IP_TX_CONTROL_PKT_COUNT = 0x2C0U, /*!< Port MAC 0 Transmit Control Packet Counter Register (PM0_TCNPn) */ 236 NETC_ETHSWT_IP_TX_DEFERRED_PKT_COUNT = 0x2D0U, /*!< Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) (PM0_TDFRn) */ 237 NETC_ETHSWT_IP_TX_MULTIPLE_COLLISIONS_COUNT = 0x2D8U, /*!< Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) (PM0_TMCOLn) */ 238 NETC_ETHSWT_IP_TX_SINGLE_COLLISION_COUNT = 0x2E0U, /*!< Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register (PM0_TSCOLn) */ 239 NETC_ETHSWT_IP_TX_LATE_COLLISION_COUNT = 0x2E8U, /*!< Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register (PM0_TLCOLn) */ 240 NETC_ETHSWT_IP_TX_EXCESSIVE_COLLISIONS_COUNT = 0x2F0U, /*!< Port MAC 0 Transmit Excessive Collisions Counter Register (PM0_TECOLn) */ 241 242 /* MAC1(PMAC) extension*/ 243 NETC_ETHSWT_IP_RX_ETH_OCTETS_COUNT_MAC1 = 0x500U, /*!< Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn) (PM1_REOCTn) */ 244 NETC_ETHSWT_IP_RX_OCTETS_COUNT_MAC1 = 0x508U, /*!< Supported by pseudo port. Port MAC 0 Receive Octets Counter(iflnOctetsn) (PM1_ROCTn) */ 245 NETC_ETHSWT_IP_RX_ALIGN_ERR_COUNT_MAC1 = 0x510U, /*!< Port MAC 1 Receive Alignment Error Counter Register(aAlignmentErrorsn) (PM1_RALNn)) */ 246 NETC_ETHSWT_IP_RX_VALID_PAUSE_FRM_COUNT_MAC1 = 0x518U, /*!< Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) (PM1_RXPFn) */ 247 NETC_ETHSWT_IP_RX_FRM_COUNT_MAC1 = 0x520U, /*!< Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn) (PM1_RFRMn) */ 248 NETC_ETHSWT_IP_RX_FRM_CHK_SEQUENCE_COUNT_MAC1 = 0x528U, /*!< Port MAC 1 Receive Frame Check Sequence Error Counter Register() (PM1_RFCSn) */ 249 NETC_ETHSWT_IP_RX_VLAN_FRM_COUNT_MAC1 = 0x530U, /*!< Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn) (PM1_RVLANn) */ 250 NETC_ETHSWT_IP_RX_FRM_ERROR_COUNT_MAC1 = 0x538U, /*!< Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn) (PM1_RERRn) */ 251 NETC_ETHSWT_IP_RX_UNICAST_FRM_COUNT_MAC1 = 0x540U, /*!< Supported by pseudo port. Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn) (PM1_RUCAn) */ 252 NETC_ETHSWT_IP_RX_MULTICAST_FRM_COUNT_MAC1 = 0x548U, /*!< Supported by pseudo port. Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn) (PM1_RMCAn) */ 253 NETC_ETHSWT_IP_RX_BROADCAST_FRM_COUNT_MAC1 = 0x550U, /*!< Supported by pseudo port. Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) (PM1_RBCAn) */ 254 NETC_ETHSWT_IP_RX_DROPPED_PKTS_COUNT_MAC1 = 0x558U, /*!< Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn) (PM1_RDRPn) */ 255 NETC_ETHSWT_IP_RX_PKTS_COUNT_MAC1 = 0x560U, /*!< Port MAC 1 Receive Packets Counter Register(etherStatsPktsn) (PM1_RPKTn) */ 256 NETC_ETHSWT_IP_RX_UNDERSIZED_PKT_COUNT_MAC1 = 0x568U, /*!< Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) (PM1_RUNDn) */ 257 NETC_ETHSWT_IP_RX_64_OCTETS_PKT_COUNT_MAC1 = 0x570U, /*!< Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) (PM1_R64n) */ 258 NETC_ETHSWT_IP_RX_127_OCTETS_PKT_COUNT_MAC1 = 0x578U, /*!< Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) (PM1_R127n) */ 259 NETC_ETHSWT_IP_RX_255_OCTETS_PKT_COUNT_MAC1 = 0x580U, /*!< Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) (PM1_R255n) */ 260 NETC_ETHSWT_IP_RX_511_OCTETS_PKT_COUNT_MAC1 = 0x588U, /*!< Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) (PM1_R511n) */ 261 NETC_ETHSWT_IP_RX_1023_OCTETS_PKT_COUNT_MAC1 = 0x590U, /*!< Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) (PM1_R1023n) */ 262 NETC_ETHSWT_IP_RX_1522_OCTETS_PKT_COUNT_MAC1 = 0x598U, /*!< Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) (PM1_R1522n) */ 263 NETC_ETHSWT_IP_RX_1523_TOMAXOCTETS_PKT_COUNT_MAC1 = 0x5A0U, /*!< Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) (PM1_R1523Xn) */ 264 NETC_ETHSWT_IP_RX_OVERSIZED_PKT_COUNT_MAC1 = 0x5A8U, /*!< Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) (PM1_ROVRn) */ 265 NETC_ETHSWT_IP_RX_JABBER_PKT_COUNT_MAC1 = 0x5B0U, /*!< Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn) (PM1_RJBRn) */ 266 NETC_ETHSWT_IP_RX_FRAGMENT_PKT_COUNT_MAC1 = 0x5B8U, /*!< Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn (PM1_RFRGn) */ 267 NETC_ETHSWT_IP_RX_CONTROL_PKT_COUNT_MAC1 = 0x5C0U, /*!< Port MAC 1 Receive Control Packet Counter Register (PM1_RCNPn) */ 268 NETC_ETHSWT_IP_RX_DROPPED_NOT_TRUNCATED_PKT_COUNT_MAC1 = 0x5C8U, /*!< Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) (PM1_RDRNTPn) */ 269 NETC_ETHSWT_IP_RX_VALID_SMALL_PKT_COUNTER_MAC1 = 0x5D0U, /*!< Port MAC 1 Receive Valid Small Packet Counter Register (PM1_RMIN63n) */ 270 271 NETC_ETHSWT_IP_TX_ETH_OCTETS_COUNT_MAC1 = 0x600U, /*!< Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn) (PM1_TEOCTn) */ 272 NETC_ETHSWT_IP_TX_OCTETS_COUNT_MAC1 = 0x608U, /*!< Supported by pseudo port. Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn) (PM1_TOCTn) */ 273 NETC_ETHSWT_IP_TX_EXCESS_DEFER_ERR_COUNT_MAC1 = 0x610U, /*!< Port MAC 1 Excess Defer Error Counter Register(aFramesWithExccessiveDeferral) (PM1_TEDFRn)) */ 274 NETC_ETHSWT_IP_TX_VALID_PAUSE_FRM_COUNT_MAC1 = 0x618U, /*!< Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) (PM1_TXPFn) */ 275 NETC_ETHSWT_IP_TX_FRM_COUNT_MAC1 = 0x620U, /*!< Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn) (PM1_TFRMn) */ 276 NETC_ETHSWT_IP_TX_FRM_CHK_SEQUENCE_COUNT_MAC1 = 0x628U, /*!< Port MAC 1 Transmit Frame Check Sequence Error Counter Register() (PM1_TFCSn) */ 277 NETC_ETHSWT_IP_TX_VLAN_FRM_COUNT_MAC1 = 0x630U, /*!< Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) (PM1_TVLANn) */ 278 NETC_ETHSWT_IP_TX_FRM_ERROR_COUNT_MAC1 = 0x638U, /*!< Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn) (PM1_TERRn) */ 279 NETC_ETHSWT_IP_TX_UNICAST_FRM_COUNT_MAC1 = 0x640U, /*!< Supported by pseudo port. Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) (PM1_TUCAn) */ 280 NETC_ETHSWT_IP_TX_MULTICAST_FRM_COUNT_MAC1 = 0x648U, /*!< Supported by pseudo port. Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) (PM1_TMCAn) */ 281 NETC_ETHSWT_IP_TX_BROADCAST_FRM_COUNT_MAC1 = 0x650U, /*!< Supported by pseudo port. Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) (PM1_TBCAn) */ 282 NETC_ETHSWT_IP_TX_PKTS_COUNT_MAC1 = 0x660U, /*!< Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn) (PM1_TPKTn) */ 283 NETC_ETHSWT_IP_TX_UNDERSIZED_PKT_COUNT_MAC1 = 0x668U, /*!< Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) (PM1_TUNDn) */ 284 NETC_ETHSWT_IP_TX_64_OCTETS_PKT_COUNT_MAC1 = 0x670U, /*!< Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) (PM1_T64n) */ 285 NETC_ETHSWT_IP_TX_127_OCTETS_PKT_COUNT_MAC1 = 0x678U, /*!< Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) (PM1_T127n) */ 286 NETC_ETHSWT_IP_TX_255_OCTETS_PKT_COUNT_MAC1 = 0x680U, /*!< Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) (PM1_T255n) */ 287 NETC_ETHSWT_IP_TX_511_OCTETS_PKT_COUNT_MAC1 = 0x688U, /*!< Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) (PM1_T511n) */ 288 NETC_ETHSWT_IP_TX_1023_OCTETS_PKT_COUNT_MAC1 = 0x690U, /*!< Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) (PM1_T1023n) */ 289 NETC_ETHSWT_IP_TX_1522_OCTETS_PKT_COUNT_MAC1 = 0x698U, /*!< Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) (PM1_T1522n) */ 290 NETC_ETHSWT_IP_TX_1523_TOMAXOCTETS_PKT_COUNT_MAC1 = 0x6A0U, /*!< Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) (PM1_T1523Xn) */ 291 NETC_ETHSWT_IP_TX_CONTROL_PKT_COUNT_MAC1 = 0x6C0U, /*!< Port MAC 1 Transmit Control Packet Counter Register (PM1_TCNPn) */ 292 NETC_ETHSWT_IP_TX_DEFERRED_PKT_COUNT_MAC1 = 0x6D0U, /*!< Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) (PM1_TDFRn) */ 293 NETC_ETHSWT_IP_TX_MULTIPLE_COLLISIONS_COUNT_MAC1 = 0x6D8U, /*!< Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) (PM1_TMCOLn) */ 294 NETC_ETHSWT_IP_TX_SINGLE_COLLISION_COUNT_MAC1 = 0x6E0U, /*!< Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register (PM1_TSCOLn) */ 295 NETC_ETHSWT_IP_TX_LATE_COLLISION_COUNT_MAC1 = 0x6E8U, /*!< Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register (PM1_TLCOLn) */ 296 NETC_ETHSWT_IP_TX_EXCESSIVE_COLLISIONS_COUNT_MAC1 = 0x6F0U /*!< Port MAC 1 Transmit Excessive Collisions Counter Register (PM1_TECOLn) */ 297 } Netc_EthSwt_Ip_SingleCounterType; 298 299 typedef enum { 300 NETC_ETHSWT_IP_PPMROCR0 = 0x80U, /*!< Port pseudo MAC receive octets counter PPMROCR0. The lower 32bits of the counter. */ 301 NETC_ETHSWT_IP_PPMROCR1 = 0x84U, /*!< Port pseudo MAC receive octets counter PPMROCR1. The upper 32bits of the counter. */ 302 NETC_ETHSWT_IP_PPMRUFCR0 = 0x88U, /*!< Port pseudo MAC receive unicast frame counter register PPMRUFCR0. The lower 32bits of the counter. */ 303 NETC_ETHSWT_IP_PPMRUFCR1 = 0x8CU, /*!< Port pseudo MAC receive unicast frame counter register PPMRUFCR1. The upper 32bits of the counter. */ 304 NETC_ETHSWT_IP_PPMRMFCR0 = 0x90U, /*!< Port pseudo MAC receive multicast frame counter register PPMRMFCR0. The lower 32bits of the counter. */ 305 NETC_ETHSWT_IP_PPMRMFCR1 = 0x94U, /*!< Port pseudo MAC receive multicast frame counter register PPMRMFCR1. The upper 32bits of the counter. */ 306 NETC_ETHSWT_IP_PPMRBFCR0 = 0x98U, /*!< Port pseudo MAC receive broadcast frame counter register PPMRBFCR0. The lower 32bits of the counter. */ 307 NETC_ETHSWT_IP_PPMRBFCR1 = 0x9CU, /*!< Port pseudo MAC receive broadcast frame counter register PPMRBFCR1. The upper 32bits of the counter. */ 308 309 NETC_ETHSWT_IP_PPMTOCR0 = 0xC0U, /*!< Port pseudo MAC transmit octets counter PPMTOCR0. The lower 32bits of the counter. */ 310 NETC_ETHSWT_IP_PPMTOCR1 = 0xC4U, /*!< Port pseudo MAC transmit octets counter PPMTOCR1. The upper 32bits of the counter. */ 311 NETC_ETHSWT_IP_PPMTUFCR0 = 0xC8U, /*!< Port pseudo MAC transmit unicast frame counter register PPMTUFCR0. The lower 32bits of the counter. */ 312 NETC_ETHSWT_IP_PPMTUFCR1 = 0xCCU, /*!< Port pseudo MAC transmit unicast frame counter register PPMTUFCR1. The upper 32bits of the counter. */ 313 NETC_ETHSWT_IP_PPMTMFCR0 = 0xD0U, /*!< Port pseudo MAC transmit multicast frame counter register PPMTMFCR0. The lower 32bits of the counter. */ 314 NETC_ETHSWT_IP_PPMTMFCR1 = 0xD4U, /*!< Port pseudo MAC transmit multicast frame counter register PPMTMFCR1. The upper 32bits of the counter. */ 315 NETC_ETHSWT_IP_PPMTBFCR0 = 0xD8U, /*!< Port pseudo MAC transmit broadcast frame counter register PPMTBFCR0. The lower 32bits of the counter. */ 316 NETC_ETHSWT_IP_PPMTBFCR1 = 0xDCU, /*!< Port pseudo MAC transmit broadcast frame counter register PPMTBFCR1. The upper 32bits of the counter. */ 317 } Netc_EthSwt_Ip_PseudoPortCounterType; 318 319 320 #if !defined(Netc_EthSwt_Ip_TimerBase) 321 #define Netc_EthSwt_Ip_TimerBase IP_NETC__TMR0_BASE 322 #endif 323 324 325 /*================================================================================================== 326 * STRUCTURES AND OTHER TYPEDEFS 327 ==================================================================================================*/ 328 329 /*================================================================================================== 330 * GLOBAL VARIABLE DECLARATIONS 331 ==================================================================================================*/ 332 333 /*================================================================================================== 334 * FUNCTION PROTOTYPES 335 ==================================================================================================*/ 336 337 #ifdef __cplusplus 338 } 339 #endif 340 341 /** @} */ 342 343 #endif /* NETC_ETHSWT_IP_CFG_DEFINES_H */ 344
