Home
last modified time | relevance | path

Searched refs:MU_TR_BTR2_MASK (Results 1 – 25 of 40) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h41355 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
41357 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h41353 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
41355 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h41353 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
41355 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h41355 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
41357 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h41355 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
41357 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h41353 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
41355 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
DMIMX8MN6_ca53.h41367 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
41369 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h40769 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
40771 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h42942 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42944 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h42942 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42944 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h42942 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42944 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h42942 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42944 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h42600 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42602 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h42600 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42602 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h42600 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42602 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
DMIMX8MM6_ca53.h42065 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42067 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h42600 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42602 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h42600 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42602 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h42600 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
42602 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_dsp.h75407 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
75410 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h68498 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
68500 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h68498 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
68500 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h68498 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
68500 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h65588 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
65590 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
DMIMX8ML8_cm7.h68498 #define MU_TR_BTR2_MASK (0xFFFFFFFFU) macro
68500 …x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)

12