Searched refs:MU_SR_GIP0_MASK (Results 1 – 1 of 1) sorted by relevance
49 #define MU_SR_GIP0_MASK (1U<<31U) macro103 kMuGenInt0 = MU_SR_GIP0_MASK, /*!< General purpose interrupt 0 pending status. */104 kMuGenInt1 = MU_SR_GIP0_MASK >> 1U, /*!< General purpose interrupt 2 pending status. */105 kMuGenInt2 = MU_SR_GIP0_MASK >> 2U, /*!< General purpose interrupt 2 pending status. */106 kMuGenInt3 = MU_SR_GIP0_MASK >> 3U, /*!< General purpose interrupt 3 pending status. */381 return (bool)(base->SR & (MU_SR_GIP0_MASK >> index)); in MU_IsGeneralIntPending()394 base->SR = (MU_SR_GIP0_MASK >> index); in MU_ClearGeneralIntPending()
