Searched refs:MUX_9_DC_1 (Results 1 – 2 of 2) sorted by relevance
3316 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency()3317 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_9_DC_1 & (uint64)MC_CGM_MUX_9_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency()3655 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> … in Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency()3656 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_9_DC_1 & (uint64)MC_CGM_MUX_9_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency()3665 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> … in Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency()3666 …Frequency /= (uint64)(((((uint64)IP_MC_CGM_4->MUX_9_DC_1 & (uint64)MC_CGM_MUX_9_DC_1_DIV_MASK) >> … in Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency()3870 …Frequency /= (uint64)(((((uint64)IP_MC_CGM_4->MUX_9_DC_1 & (uint64)MC_CGM_MUX_9_DC_1_DIV_MASK) >> … in Clock_Ip_Get_QSPI1_CLK_Frequency()
157 …__IO uint32_t MUX_9_DC_1; /**< Clock Mux 9 Divider 1 Control Register, offs… member
