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Searched refs:MUX_9_CSS (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2381 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_CTU_CLK_Frequency()
2963 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P0_CTU_PER_CLK_Frequency()
2983 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency()
3295 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency()
3305 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency()
3315 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency()
3654 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency()
3664 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency()
3868 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_QSPI1_CLK_Frequency()
3907 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P4_SDHC_CLK_Frequency()
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/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h133 …__I uint32_t MUX_9_CSS; /**< Clock Mux 9 Select Status Register, offset: … member
/hal_nxp-latest/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c2854 …uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_M… in Clock_Ip_Get_EMAC_TS_CLK_Frequency()
3728 …uint32 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_M… in Clock_Ip_Get_GMAC_TS_CLK_Frequency()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h155 …__I uint32_t MUX_9_CSS; /**< Clock Mux 9 Select Status Register, offset: … member