Searched refs:MUX_8_DC_1 (Results 1 – 2 of 2) sorted by relevance
3336 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency()3337 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_8_DC_1 & (uint64)MC_CGM_MUX_8_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency()3346 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH1_PS_TX_CLK_Frequency()3347 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_8_DC_1 & (uint64)MC_CGM_MUX_8_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_ETH1_PS_TX_CLK_Frequency()
151 …__IO uint32_t MUX_8_DC_1; /**< Clock Mux 8 Divider 1 Control Register, offs… member
