Searched refs:MUX_8_DC_0 (Results 1 – 4 of 4) sorted by relevance
2195 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> … in Clock_Ip_Get_GLB_LBIST_CLK_Frequency()2196 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_8_DC_0 & (uint64)MC_CGM_MUX_8_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_GLB_LBIST_CLK_Frequency()2918 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> … in Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency()2919 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_8_DC_0 & (uint64)MC_CGM_MUX_8_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency()2929 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_8_DC_0 & (uint64)MC_CGM_MUX_8_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_LIN6_CLK_Frequency()2939 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_8_DC_0 & (uint64)MC_CGM_MUX_8_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_LIN7_CLK_Frequency()2949 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_8_DC_0 & (uint64)MC_CGM_MUX_8_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_LIN8_CLK_Frequency()3326 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency()3327 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_8_DC_0 & (uint64)MC_CGM_MUX_8_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency()3446 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> … in Clock_Ip_Get_P4_LIN_CLK_Frequency()[all …]
2872 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_EMAC_TX_CLK_Frequency()2873 …Frequency /= (((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT… in Clock_Ip_Get_EMAC_TX_CLK_Frequency()3719 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_GMAC0_TX_CLK_Frequency()3720 …Frequency /= (((IP_MC_CGM->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT… in Clock_Ip_Get_GMAC0_TX_CLK_Frequency()
129 …__IO uint32_t MUX_8_DC_0; /**< Clock Mux 8 Divider 0 Control Register, offs… member
150 …__IO uint32_t MUX_8_DC_0; /**< Clock Mux 8 Divider 0 Control Register, offs… member
