Searched refs:MUX_7_DC_1 (Results 1 – 2 of 2) sorted by relevance
1807 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> … in Clock_Ip_Get_MSCDSPI_CLK_Frequency()1808 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_7_DC_1 & (uint64)MC_CGM_MUX_7_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_MSCDSPI_CLK_Frequency()2974 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> … in Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency()2975 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_7_DC_1 & (uint64)MC_CGM_MUX_7_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency()3266 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency()3267 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_7_DC_1 & (uint64)MC_CGM_MUX_7_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency()
142 …__IO uint32_t MUX_7_DC_1; /**< Clock Mux 7 Divider 1 Control Register, offs… member
