Searched refs:MUX_6_DC_1 (Results 1 – 2 of 2) sorted by relevance
3276 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency()3277 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_6_DC_1 & (uint64)MC_CGM_MUX_6_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency()3286 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DE_MASK) >> … in Clock_Ip_Get_ETH0_PS_TX_CLK_Frequency()3287 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_6_DC_1 & (uint64)MC_CGM_MUX_6_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_ETH0_PS_TX_CLK_Frequency()
136 …__IO uint32_t MUX_6_DC_1; /**< Clock Mux 6 Divider 1 Control Register, offs… member
