Searched refs:MUX_5_DC_1 (Results 1 – 2 of 2) sorted by relevance
129 …__IO uint32_t MUX_5_DC_1; /**< Clock Mux 5 Divider 1 Control Register, offs… member
3729 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_1 & MC_CGM_MUX_5_DC_1_DE_MASK) >> … in Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency()3730 …Frequency /= (uint64)((((uint64)IP_MC_CGM_5->MUX_5_DC_1 & (uint64)MC_CGM_MUX_5_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency()
