Searched refs:MUX_5_DC_0 (Results 1 – 4 of 4) sorted by relevance
3226 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH_TS_CLK_Frequency()3227 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_5_DC_0 & (uint64)MC_CGM_MUX_5_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_ETH_TS_CLK_Frequency()3236 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency()3237 …Frequency /= (uint64)(((((uint64)IP_MC_CGM_1->MUX_5_DC_0 & (uint64)MC_CGM_MUX_5_DC_0_DIV_MASK) >> … in Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency()3719 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> … in Clock_Ip_Get_P5_AE_CLK_Frequency()3720 …Frequency /= (uint64)((((uint64)IP_MC_CGM_5->MUX_5_DC_0 & (uint64)MC_CGM_MUX_5_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_P5_AE_CLK_Frequency()
114 …__IO uint32_t MUX_5_DC_0; /**< Clock Mux 5 Divider 0 Control Register, offs… member
2142 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency()2143 …Frequency /= (((IP_MC_CGM->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT… in Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency()
128 …__IO uint32_t MUX_5_DC_0; /**< Clock Mux 5 Divider 0 Control Register, offs… member
