Searched refs:MUX_3_DC_1 (Results 1 – 2 of 2) sorted by relevance
3115 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency()3116 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_3_DC_1 & (uint64)MC_CGM_MUX_3_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency()3549 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency()3550 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_3_DC_1 & (uint64)MC_CGM_MUX_3_DC_1_DIV_MASK) >> (… in Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency()
112 …__IO uint32_t MUX_3_DC_1; /**< Clock Mux 3 Divider 1 Control Register, offs… member
