Searched refs:MUX_2_DC_5 (Results 1 – 2 of 2) sorted by relevance
3094 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency()3095 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_2_DC_5 & (uint64)MC_CGM_MUX_2_DC_5_DIV_MASK) >> (… in Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency()3104 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency()3105 …Frequency /= (uint64)(((((uint64)IP_MC_CGM_0->MUX_2_DC_5 & (uint64)MC_CGM_MUX_2_DC_5_DIV_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency()3517 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency()3518 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_2_DC_5 & (uint64)MC_CGM_MUX_2_DC_5_DIV_MASK) >> (… in Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency()3527 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency()3528 …Frequency /= (uint64)(((((uint64)IP_MC_CGM_4->MUX_2_DC_5 & (uint64)MC_CGM_MUX_2_DC_5_DIV_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency()
106 …__IO uint32_t MUX_2_DC_5; /**< Clock Mux 2 Divider 5 Control Register, offs… member
