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Searched refs:MUX_1_DC_0 (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c1907 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_REG_INTF_CLK_Frequency()
1908 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_1_DC_0 & (uint64)MC_CGM_MUX_1_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_P0_REG_INTF_CLK_Frequency()
1958 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> … in Clock_Ip_Get_P1_REG_INTF_CLK_Frequency()
1959 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_1_DC_0 & (uint64)MC_CGM_MUX_1_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_P1_REG_INTF_CLK_Frequency()
1974 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_2->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> … in Clock_Ip_Get_P2_REG_INTF_CLK_Frequency()
1975 …Frequency /= (uint64)((((uint64)IP_MC_CGM_2->MUX_1_DC_0 & (uint64)MC_CGM_MUX_1_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_P2_REG_INTF_CLK_Frequency()
2007 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> … in Clock_Ip_Get_P5_REG_INTF_CLK_Frequency()
2008 …Frequency /= (uint64)((((uint64)IP_MC_CGM_5->MUX_1_DC_0 & (uint64)MC_CGM_MUX_1_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_P5_REG_INTF_CLK_Frequency()
2430 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> … in Clock_Ip_Get_DMAMUX0_CLK_Frequency()
2431 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_1_DC_0 & (uint64)MC_CGM_MUX_1_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_DMAMUX0_CLK_Frequency()
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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_RTU_MC_CGM.h92 …__IO uint32_t MUX_1_DC_0; /**< Clock Mux 1 Divider 0 Control Register, offs… member
DS32Z2_MC_CGM.h95 …__IO uint32_t MUX_1_DC_0; /**< Clock Mux 1 Divider 0 Control Register, offs… member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h94 …__IO uint32_t MUX_1_DC_0; /**< Clock Mux 1 Divider 0 Control Register, offs… member
/hal_nxp-latest/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c3642 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_STMA_CLK_Frequency()
3643 …Frequency /= (((IP_MC_CGM->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT… in Clock_Ip_Get_STMA_CLK_Frequency()