Searched refs:MUX_10_DC_0 (Results 1 – 4 of 4) sorted by relevance
3437 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DE_MASK) >> … in Clock_Ip_Get_QSPI_2XSFIF_CLK_Frequency()3438 …Frequency /= ((((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_S… in Clock_Ip_Get_QSPI_2XSFIF_CLK_Frequency()3476 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DE_MASK) >> … in Clock_Ip_Get_QSPI_SFCK_CLK_Frequency()3477 …Frequency /= (((IP_MC_CGM->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_SH… in Clock_Ip_Get_QSPI_SFCK_CLK_Frequency()
139 …__IO uint32_t MUX_10_DC_0; /**< Clock Mux 10 Divider 0 Control Register, off… member
163 …__IO uint32_t MUX_10_DC_0; /**< Clock Mux 10 Divider 0 Control Register, off… member
2481 …Frequency /= (uint64)((((uint64)IP_MC_CGM_0->MUX_10_DC_0 & (uint64)MC_CGM_MUX_10_DC_0_DIV_MASK) >>… in Clock_Ip_Get_CLKOUT0_CLK_Frequency()2498 …Frequency /= (uint64)((((uint64)IP_MC_CGM_1->MUX_10_DC_0 & (uint64)MC_CGM_MUX_10_DC_0_DIV_MASK) >>… in Clock_Ip_Get_CLKOUT1_CLK_Frequency()
