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Searched refs:MUX_0_CSC (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Data.c2664 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_0->MUX_0_CSC),
2683 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_1->MUX_0_CSC),
2702 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_2->MUX_0_CSC),
2721 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_3->MUX_0_CSC),
2739 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_0_CSC),
2757 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_5->MUX_0_CSC),
2775 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_6->MUX_0_CSC),
2793 { (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU0__MC_CGM->MUX_0_CSC),
2811 { (Clock_Ip_CgmMuxType*)(&CLOCK_IP_RTU1__MC_CGM->MUX_0_CSC),
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_RTU_MC_CGM.h85 …__IO uint32_t MUX_0_CSC; /**< Clock Mux 0 Select Control Register, offset:… member
DS32Z2_MC_CGM.h87 …__IO uint32_t MUX_0_CSC; /**< Clock Mux 0 Select Control Register, offset:… member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h79 …__IO uint32_t MUX_0_CSC; /**< Clock Mux 0 Select Control Register, offset:… member
/hal_nxp-latest/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Data.c3315 (Clock_Ip_CgmMuxType*)(&(IP_MC_CGM->MUX_0_CSC)),