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Searched refs:MSCR (Results 1 – 25 of 92) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/enet/
Dfsl_enet.h972 return (0U != (base->MSCR & 0x7EU)); in ENET_GetSMI()
Dfsl_enet.c1222 base->MSCR = mscr; in ENET_SetSMI()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_ENET.h86 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SIUL2.h102 …__IO uint32_t MSCR[SIUL2_MSCR_COUNT]; /**< SIUL2 Multiplexed Signal Configuration Regis… member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_SIUL2.h101 …__IO uint32_t MSCR[SIUL2_MSCR_COUNT]; /**< SIUL2 Multiplexed Signal Configuration Regis… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h9721 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h9708 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/
DMKV58F24.h11963 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h8455 …__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x… member
8596 #define ENET_MSCR_REG(base) ((base)->MSCR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h11350 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/
DMK66F18.h11350 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h13097 …__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x… member
13238 #define ENET_MSCR_REG(base) ((base)->MSCR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h16513 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h16533 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h17563 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h18634 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h18348 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h18636 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h19002 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h24653 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h24651 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h24651 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h24653 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h19866 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h24653 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member

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