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Searched refs:MSCM_OCMDR5_OCMW_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h25716 #define MSCM_OCMDR5_OCMW_MASK (0xE0000U) macro
25726 … (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMW_SHIFT)) & MSCM_OCMDR5_OCMW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h27885 #define MSCM_OCMDR5_OCMW_MASK (0xE0000U) macro
27895 … (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMW_SHIFT)) & MSCM_OCMDR5_OCMW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h29099 #define MSCM_OCMDR5_OCMW_MASK (0xE0000U) macro
29109 … (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMW_SHIFT)) & MSCM_OCMDR5_OCMW_MASK)
DMCXW727C_cm33_core1.h36851 #define MSCM_OCMDR5_OCMW_MASK (0xE0000U) macro
36861 … (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR5_OCMW_SHIFT)) & MSCM_OCMDR5_OCMW_MASK)