1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MSCM.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_MSCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MSCM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MSCM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MSCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MSCM - Size of Registers Arrays */ 72 #define MSCM_IRSPRC_COUNT 789u 73 74 /** MSCM - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t CPXTYPE; /**< Core Processor x Type, offset: 0x0 */ 77 __I uint32_t CPXNUM; /**< Core Processor x Number, offset: 0x4 */ 78 __I uint32_t CPXREV; /**< Core Processor x Revision, offset: 0x8 */ 79 __I uint32_t CPXCFG0; /**< Core Processor x Configuration 0, offset: 0xC */ 80 __I uint32_t CPXCFG1; /**< Core or Cluster Processor x Configuration 1, offset: 0x10 */ 81 __I uint32_t CPXCFG2; /**< Core Processor x Configuration 2, offset: 0x14 */ 82 __I uint32_t CPXCFG3; /**< Core Processor x Configuration 3, offset: 0x18 */ 83 uint8_t RESERVED_0[4]; 84 __I uint32_t CP0TYPE; /**< Cluster Processor 0 Type, offset: 0x20 */ 85 __I uint32_t CP0NUM; /**< Cluster Processor 0 Number, offset: 0x24 */ 86 __I uint32_t CP0REV; /**< Core Processor 0 Revision, offset: 0x28 */ 87 __I uint32_t CP0CFG0; /**< Core Processor 0 Configuration 0, offset: 0x2C */ 88 __I uint32_t CP0CFG1; /**< Cluster Processor 0 Configuration 1, offset: 0x30 */ 89 __I uint32_t CP0CFG2; /**< Core Processor 0 Configuration 2, offset: 0x34 */ 90 __I uint32_t CP0CFG3; /**< Core Processor 0 Configuration 3, offset: 0x38 */ 91 uint8_t RESERVED_1[4]; 92 __I uint32_t CP1TYPE; /**< Cluster Processor 1 Type, offset: 0x40 */ 93 __I uint32_t CP1NUM; /**< Cluster Processor 1 Number, offset: 0x44 */ 94 __I uint32_t CP1REV; /**< Core Processor 1 Revision, offset: 0x48 */ 95 __I uint32_t CP1CFG0; /**< Core Processor 1 Configuration 0, offset: 0x4C */ 96 __I uint32_t CP1CFG1; /**< Cluster Processor 1 Configuration 1, offset: 0x50 */ 97 __I uint32_t CP1CFG2; /**< Core Processor 1 Configuration 2, offset: 0x54 */ 98 __I uint32_t CP1CFG3; /**< Core Processor 1 Configuration 3, offset: 0x58 */ 99 uint8_t RESERVED_2[4]; 100 __I uint32_t CP2TYPE; /**< Core Processor 2 Type, offset: 0x60 */ 101 __I uint32_t CP2NUM; /**< Core Processor 2 Number, offset: 0x64 */ 102 __I uint32_t CP2REV; /**< Core Processor 2 Revision, offset: 0x68 */ 103 __I uint32_t CP2CFG0; /**< Core Processor 2 Configuration 0, offset: 0x6C */ 104 __I uint32_t CP2CFG1; /**< Core Processor 2 Configuration 1, offset: 0x70 */ 105 __I uint32_t CP2CFG2; /**< Core Processor 2 Configuration 2, offset: 0x74 */ 106 __I uint32_t CP2CFG3; /**< Core Processor 2 Configuration 3, offset: 0x78 */ 107 uint8_t RESERVED_3[4]; 108 __I uint32_t CP3TYPE; /**< Core Processor 3 Type, offset: 0x80 */ 109 __I uint32_t CP3NUM; /**< Core Processor 3 Number, offset: 0x84 */ 110 __I uint32_t CP3REV; /**< Core Processor 3 Revision, offset: 0x88 */ 111 __I uint32_t CP3CFG0; /**< Core Processor 3 Configuration 0, offset: 0x8C */ 112 __I uint32_t CP3CFG1; /**< Core Processor 3 Configuration 1, offset: 0x90 */ 113 __I uint32_t CP3CFG2; /**< Core Processor 3 Configuration 2, offset: 0x94 */ 114 __I uint32_t CP3CFG3; /**< Core Processor 3 Configuration 3, offset: 0x98 */ 115 uint8_t RESERVED_4[2020]; 116 __IO uint16_t IRSPRC[MSCM_IRSPRC_COUNT]; /**< Interrupt Router Shared Peripheral Routing Control, array offset: 0x880, array step: 0x2 */ 117 } MSCM_Type, *MSCM_MemMapPtr; 118 119 /** Number of instances of the MSCM module. */ 120 #define MSCM_INSTANCE_COUNT (1u) 121 122 /* MSCM - Peripheral instance base addresses */ 123 /** Peripheral MSCM base address */ 124 #define IP_MSCM_BASE (0x419A0000u) 125 /** Peripheral MSCM base pointer */ 126 #define IP_MSCM ((MSCM_Type *)IP_MSCM_BASE) 127 /** Array initializer of MSCM peripheral base addresses */ 128 #define IP_MSCM_BASE_ADDRS { IP_MSCM_BASE } 129 /** Array initializer of MSCM peripheral base pointers */ 130 #define IP_MSCM_BASE_PTRS { IP_MSCM } 131 132 /* ---------------------------------------------------------------------------- 133 -- MSCM Register Masks 134 ---------------------------------------------------------------------------- */ 135 136 /*! 137 * @addtogroup MSCM_Register_Masks MSCM Register Masks 138 * @{ 139 */ 140 141 /*! @name CPXTYPE - Core Processor x Type */ 142 /*! @{ */ 143 144 #define MSCM_CPXTYPE_PERSONALITY_MASK (0xFFFFFFFFU) 145 #define MSCM_CPXTYPE_PERSONALITY_SHIFT (0U) 146 #define MSCM_CPXTYPE_PERSONALITY_WIDTH (32U) 147 #define MSCM_CPXTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXTYPE_PERSONALITY_SHIFT)) & MSCM_CPXTYPE_PERSONALITY_MASK) 148 /*! @} */ 149 150 /*! @name CPXNUM - Core Processor x Number */ 151 /*! @{ */ 152 153 #define MSCM_CPXNUM_CPN_MASK (0xFU) 154 #define MSCM_CPXNUM_CPN_SHIFT (0U) 155 #define MSCM_CPXNUM_CPN_WIDTH (4U) 156 #define MSCM_CPXNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXNUM_CPN_SHIFT)) & MSCM_CPXNUM_CPN_MASK) 157 /*! @} */ 158 159 /*! @name CPXREV - Core Processor x Revision */ 160 /*! @{ */ 161 162 #define MSCM_CPXREV_RYPZ_MASK (0xFFU) 163 #define MSCM_CPXREV_RYPZ_SHIFT (0U) 164 #define MSCM_CPXREV_RYPZ_WIDTH (8U) 165 #define MSCM_CPXREV_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXREV_RYPZ_SHIFT)) & MSCM_CPXREV_RYPZ_MASK) 166 /*! @} */ 167 168 /*! @name CPXCFG0 - Core Processor x Configuration 0 */ 169 /*! @{ */ 170 171 #define MSCM_CPXCFG0_DCWY_MASK (0xFFU) 172 #define MSCM_CPXCFG0_DCWY_SHIFT (0U) 173 #define MSCM_CPXCFG0_DCWY_WIDTH (8U) 174 #define MSCM_CPXCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCWY_SHIFT)) & MSCM_CPXCFG0_DCWY_MASK) 175 176 #define MSCM_CPXCFG0_DCSZ_MASK (0xFF00U) 177 #define MSCM_CPXCFG0_DCSZ_SHIFT (8U) 178 #define MSCM_CPXCFG0_DCSZ_WIDTH (8U) 179 #define MSCM_CPXCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_DCSZ_SHIFT)) & MSCM_CPXCFG0_DCSZ_MASK) 180 181 #define MSCM_CPXCFG0_ICWY_MASK (0xFF0000U) 182 #define MSCM_CPXCFG0_ICWY_SHIFT (16U) 183 #define MSCM_CPXCFG0_ICWY_WIDTH (8U) 184 #define MSCM_CPXCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICWY_SHIFT)) & MSCM_CPXCFG0_ICWY_MASK) 185 186 #define MSCM_CPXCFG0_ICSZ_MASK (0xFF000000U) 187 #define MSCM_CPXCFG0_ICSZ_SHIFT (24U) 188 #define MSCM_CPXCFG0_ICSZ_WIDTH (8U) 189 #define MSCM_CPXCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK) 190 /*! @} */ 191 192 /*! @name CPXCFG1 - Core or Cluster Processor x Configuration 1 */ 193 /*! @{ */ 194 195 #define MSCM_CPXCFG1_L2WY_MASK (0xFF0000U) 196 #define MSCM_CPXCFG1_L2WY_SHIFT (16U) 197 #define MSCM_CPXCFG1_L2WY_WIDTH (8U) 198 #define MSCM_CPXCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2WY_SHIFT)) & MSCM_CPXCFG1_L2WY_MASK) 199 200 #define MSCM_CPXCFG1_L2SZ_MASK (0xFF000000U) 201 #define MSCM_CPXCFG1_L2SZ_SHIFT (24U) 202 #define MSCM_CPXCFG1_L2SZ_WIDTH (8U) 203 #define MSCM_CPXCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG1_L2SZ_SHIFT)) & MSCM_CPXCFG1_L2SZ_MASK) 204 /*! @} */ 205 206 /*! @name CPXCFG2 - Core Processor x Configuration 2 */ 207 /*! @{ */ 208 209 #define MSCM_CPXCFG2_ITCM_MASK (0xFFFFU) 210 #define MSCM_CPXCFG2_ITCM_SHIFT (0U) 211 #define MSCM_CPXCFG2_ITCM_WIDTH (16U) 212 #define MSCM_CPXCFG2_ITCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_ITCM_SHIFT)) & MSCM_CPXCFG2_ITCM_MASK) 213 214 #define MSCM_CPXCFG2_TCM_MASK (0xFFFF0000U) 215 #define MSCM_CPXCFG2_TCM_SHIFT (16U) 216 #define MSCM_CPXCFG2_TCM_WIDTH (16U) 217 #define MSCM_CPXCFG2_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG2_TCM_SHIFT)) & MSCM_CPXCFG2_TCM_MASK) 218 /*! @} */ 219 220 /*! @name CPXCFG3 - Core Processor x Configuration 3 */ 221 /*! @{ */ 222 223 #define MSCM_CPXCFG3_FPU_MASK (0x1U) 224 #define MSCM_CPXCFG3_FPU_SHIFT (0U) 225 #define MSCM_CPXCFG3_FPU_WIDTH (1U) 226 #define MSCM_CPXCFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_FPU_SHIFT)) & MSCM_CPXCFG3_FPU_MASK) 227 228 #define MSCM_CPXCFG3_SIMD_MASK (0x2U) 229 #define MSCM_CPXCFG3_SIMD_SHIFT (1U) 230 #define MSCM_CPXCFG3_SIMD_WIDTH (1U) 231 #define MSCM_CPXCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_SIMD_SHIFT)) & MSCM_CPXCFG3_SIMD_MASK) 232 233 #define MSCM_CPXCFG3_MMU_MASK (0x4U) 234 #define MSCM_CPXCFG3_MMU_SHIFT (2U) 235 #define MSCM_CPXCFG3_MMU_WIDTH (1U) 236 #define MSCM_CPXCFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_MMU_SHIFT)) & MSCM_CPXCFG3_MMU_MASK) 237 238 #define MSCM_CPXCFG3_CMP_MASK (0x8U) 239 #define MSCM_CPXCFG3_CMP_SHIFT (3U) 240 #define MSCM_CPXCFG3_CMP_WIDTH (1U) 241 #define MSCM_CPXCFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CMP_SHIFT)) & MSCM_CPXCFG3_CMP_MASK) 242 243 #define MSCM_CPXCFG3_CPY_MASK (0x10U) 244 #define MSCM_CPXCFG3_CPY_SHIFT (4U) 245 #define MSCM_CPXCFG3_CPY_WIDTH (1U) 246 #define MSCM_CPXCFG3_CPY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG3_CPY_SHIFT)) & MSCM_CPXCFG3_CPY_MASK) 247 /*! @} */ 248 249 /*! @name CP0TYPE - Cluster Processor 0 Type */ 250 /*! @{ */ 251 252 #define MSCM_CP0TYPE_PERSONALITY_MASK (0xFFFFFFFFU) 253 #define MSCM_CP0TYPE_PERSONALITY_SHIFT (0U) 254 #define MSCM_CP0TYPE_PERSONALITY_WIDTH (32U) 255 #define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_PERSONALITY_SHIFT)) & MSCM_CP0TYPE_PERSONALITY_MASK) 256 /*! @} */ 257 258 /*! @name CP0NUM - Cluster Processor 0 Number */ 259 /*! @{ */ 260 261 #define MSCM_CP0NUM_CPN_MASK (0xFU) 262 #define MSCM_CP0NUM_CPN_SHIFT (0U) 263 #define MSCM_CP0NUM_CPN_WIDTH (4U) 264 #define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0NUM_CPN_SHIFT)) & MSCM_CP0NUM_CPN_MASK) 265 /*! @} */ 266 267 /*! @name CP0REV - Core Processor 0 Revision */ 268 /*! @{ */ 269 270 #define MSCM_CP0REV_RYPZ_MASK (0xFFU) 271 #define MSCM_CP0REV_RYPZ_SHIFT (0U) 272 #define MSCM_CP0REV_RYPZ_WIDTH (8U) 273 #define MSCM_CP0REV_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0REV_RYPZ_SHIFT)) & MSCM_CP0REV_RYPZ_MASK) 274 /*! @} */ 275 276 /*! @name CP0CFG0 - Core Processor 0 Configuration 0 */ 277 /*! @{ */ 278 279 #define MSCM_CP0CFG0_DCWY_MASK (0xFFU) 280 #define MSCM_CP0CFG0_DCWY_SHIFT (0U) 281 #define MSCM_CP0CFG0_DCWY_WIDTH (8U) 282 #define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCWY_SHIFT)) & MSCM_CP0CFG0_DCWY_MASK) 283 284 #define MSCM_CP0CFG0_DCSZ_MASK (0xFF00U) 285 #define MSCM_CP0CFG0_DCSZ_SHIFT (8U) 286 #define MSCM_CP0CFG0_DCSZ_WIDTH (8U) 287 #define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCSZ_SHIFT)) & MSCM_CP0CFG0_DCSZ_MASK) 288 289 #define MSCM_CP0CFG0_ICWY_MASK (0xFF0000U) 290 #define MSCM_CP0CFG0_ICWY_SHIFT (16U) 291 #define MSCM_CP0CFG0_ICWY_WIDTH (8U) 292 #define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICWY_SHIFT)) & MSCM_CP0CFG0_ICWY_MASK) 293 294 #define MSCM_CP0CFG0_ICSZ_MASK (0xFF000000U) 295 #define MSCM_CP0CFG0_ICSZ_SHIFT (24U) 296 #define MSCM_CP0CFG0_ICSZ_WIDTH (8U) 297 #define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICSZ_SHIFT)) & MSCM_CP0CFG0_ICSZ_MASK) 298 /*! @} */ 299 300 /*! @name CP0CFG1 - Cluster Processor 0 Configuration 1 */ 301 /*! @{ */ 302 303 #define MSCM_CP0CFG1_L2WY_MASK (0xFF0000U) 304 #define MSCM_CP0CFG1_L2WY_SHIFT (16U) 305 #define MSCM_CP0CFG1_L2WY_WIDTH (8U) 306 #define MSCM_CP0CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2WY_SHIFT)) & MSCM_CP0CFG1_L2WY_MASK) 307 308 #define MSCM_CP0CFG1_L2SZ_MASK (0xFF000000U) 309 #define MSCM_CP0CFG1_L2SZ_SHIFT (24U) 310 #define MSCM_CP0CFG1_L2SZ_WIDTH (8U) 311 #define MSCM_CP0CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2SZ_SHIFT)) & MSCM_CP0CFG1_L2SZ_MASK) 312 /*! @} */ 313 314 /*! @name CP0CFG2 - Core Processor 0 Configuration 2 */ 315 /*! @{ */ 316 317 #define MSCM_CP0CFG2_TCM_MASK (0xFFFF0000U) 318 #define MSCM_CP0CFG2_TCM_SHIFT (16U) 319 #define MSCM_CP0CFG2_TCM_WIDTH (16U) 320 #define MSCM_CP0CFG2_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_TCM_SHIFT)) & MSCM_CP0CFG2_TCM_MASK) 321 /*! @} */ 322 323 /*! @name CP0CFG3 - Core Processor 0 Configuration 3 */ 324 /*! @{ */ 325 326 #define MSCM_CP0CFG3_FPU_MASK (0x1U) 327 #define MSCM_CP0CFG3_FPU_SHIFT (0U) 328 #define MSCM_CP0CFG3_FPU_WIDTH (1U) 329 #define MSCM_CP0CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_FPU_SHIFT)) & MSCM_CP0CFG3_FPU_MASK) 330 331 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) 332 #define MSCM_CP0CFG3_SIMD_SHIFT (1U) 333 #define MSCM_CP0CFG3_SIMD_WIDTH (1U) 334 #define MSCM_CP0CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK) 335 336 #define MSCM_CP0CFG3_MMU_MASK (0x4U) 337 #define MSCM_CP0CFG3_MMU_SHIFT (2U) 338 #define MSCM_CP0CFG3_MMU_WIDTH (1U) 339 #define MSCM_CP0CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_MMU_SHIFT)) & MSCM_CP0CFG3_MMU_MASK) 340 341 #define MSCM_CP0CFG3_CMP_MASK (0x8U) 342 #define MSCM_CP0CFG3_CMP_SHIFT (3U) 343 #define MSCM_CP0CFG3_CMP_WIDTH (1U) 344 #define MSCM_CP0CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_CMP_SHIFT)) & MSCM_CP0CFG3_CMP_MASK) 345 346 #define MSCM_CP0CFG3_CPY_MASK (0x10U) 347 #define MSCM_CP0CFG3_CPY_SHIFT (4U) 348 #define MSCM_CP0CFG3_CPY_WIDTH (1U) 349 #define MSCM_CP0CFG3_CPY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_CPY_SHIFT)) & MSCM_CP0CFG3_CPY_MASK) 350 /*! @} */ 351 352 /*! @name CP1TYPE - Cluster Processor 1 Type */ 353 /*! @{ */ 354 355 #define MSCM_CP1TYPE_PERSONALITY_MASK (0xFFFFFFFFU) 356 #define MSCM_CP1TYPE_PERSONALITY_SHIFT (0U) 357 #define MSCM_CP1TYPE_PERSONALITY_WIDTH (32U) 358 #define MSCM_CP1TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1TYPE_PERSONALITY_SHIFT)) & MSCM_CP1TYPE_PERSONALITY_MASK) 359 /*! @} */ 360 361 /*! @name CP1NUM - Cluster Processor 1 Number */ 362 /*! @{ */ 363 364 #define MSCM_CP1NUM_CPN_MASK (0xFU) 365 #define MSCM_CP1NUM_CPN_SHIFT (0U) 366 #define MSCM_CP1NUM_CPN_WIDTH (4U) 367 #define MSCM_CP1NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1NUM_CPN_SHIFT)) & MSCM_CP1NUM_CPN_MASK) 368 /*! @} */ 369 370 /*! @name CP1REV - Core Processor 1 Revision */ 371 /*! @{ */ 372 373 #define MSCM_CP1REV_RYPZ_MASK (0xFFU) 374 #define MSCM_CP1REV_RYPZ_SHIFT (0U) 375 #define MSCM_CP1REV_RYPZ_WIDTH (8U) 376 #define MSCM_CP1REV_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1REV_RYPZ_SHIFT)) & MSCM_CP1REV_RYPZ_MASK) 377 /*! @} */ 378 379 /*! @name CP1CFG0 - Core Processor 1 Configuration 0 */ 380 /*! @{ */ 381 382 #define MSCM_CP1CFG0_DCWY_MASK (0xFFU) 383 #define MSCM_CP1CFG0_DCWY_SHIFT (0U) 384 #define MSCM_CP1CFG0_DCWY_WIDTH (8U) 385 #define MSCM_CP1CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_DCWY_SHIFT)) & MSCM_CP1CFG0_DCWY_MASK) 386 387 #define MSCM_CP1CFG0_DCSZ_MASK (0xFF00U) 388 #define MSCM_CP1CFG0_DCSZ_SHIFT (8U) 389 #define MSCM_CP1CFG0_DCSZ_WIDTH (8U) 390 #define MSCM_CP1CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_DCSZ_SHIFT)) & MSCM_CP1CFG0_DCSZ_MASK) 391 392 #define MSCM_CP1CFG0_ICWY_MASK (0xFF0000U) 393 #define MSCM_CP1CFG0_ICWY_SHIFT (16U) 394 #define MSCM_CP1CFG0_ICWY_WIDTH (8U) 395 #define MSCM_CP1CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_ICWY_SHIFT)) & MSCM_CP1CFG0_ICWY_MASK) 396 397 #define MSCM_CP1CFG0_ICSZ_MASK (0xFF000000U) 398 #define MSCM_CP1CFG0_ICSZ_SHIFT (24U) 399 #define MSCM_CP1CFG0_ICSZ_WIDTH (8U) 400 #define MSCM_CP1CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG0_ICSZ_SHIFT)) & MSCM_CP1CFG0_ICSZ_MASK) 401 /*! @} */ 402 403 /*! @name CP1CFG1 - Cluster Processor 1 Configuration 1 */ 404 /*! @{ */ 405 406 #define MSCM_CP1CFG1_L2WY_MASK (0xFF0000U) 407 #define MSCM_CP1CFG1_L2WY_SHIFT (16U) 408 #define MSCM_CP1CFG1_L2WY_WIDTH (8U) 409 #define MSCM_CP1CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG1_L2WY_SHIFT)) & MSCM_CP1CFG1_L2WY_MASK) 410 411 #define MSCM_CP1CFG1_L2SZ_MASK (0xFF000000U) 412 #define MSCM_CP1CFG1_L2SZ_SHIFT (24U) 413 #define MSCM_CP1CFG1_L2SZ_WIDTH (8U) 414 #define MSCM_CP1CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG1_L2SZ_SHIFT)) & MSCM_CP1CFG1_L2SZ_MASK) 415 /*! @} */ 416 417 /*! @name CP1CFG2 - Core Processor 1 Configuration 2 */ 418 /*! @{ */ 419 420 #define MSCM_CP1CFG2_TCM_MASK (0xFFFF0000U) 421 #define MSCM_CP1CFG2_TCM_SHIFT (16U) 422 #define MSCM_CP1CFG2_TCM_WIDTH (16U) 423 #define MSCM_CP1CFG2_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG2_TCM_SHIFT)) & MSCM_CP1CFG2_TCM_MASK) 424 /*! @} */ 425 426 /*! @name CP1CFG3 - Core Processor 1 Configuration 3 */ 427 /*! @{ */ 428 429 #define MSCM_CP1CFG3_FPU_MASK (0x1U) 430 #define MSCM_CP1CFG3_FPU_SHIFT (0U) 431 #define MSCM_CP1CFG3_FPU_WIDTH (1U) 432 #define MSCM_CP1CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_FPU_SHIFT)) & MSCM_CP1CFG3_FPU_MASK) 433 434 #define MSCM_CP1CFG3_SIMD_MASK (0x2U) 435 #define MSCM_CP1CFG3_SIMD_SHIFT (1U) 436 #define MSCM_CP1CFG3_SIMD_WIDTH (1U) 437 #define MSCM_CP1CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_SIMD_SHIFT)) & MSCM_CP1CFG3_SIMD_MASK) 438 439 #define MSCM_CP1CFG3_MMU_MASK (0x4U) 440 #define MSCM_CP1CFG3_MMU_SHIFT (2U) 441 #define MSCM_CP1CFG3_MMU_WIDTH (1U) 442 #define MSCM_CP1CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_MMU_SHIFT)) & MSCM_CP1CFG3_MMU_MASK) 443 444 #define MSCM_CP1CFG3_CMP_MASK (0x8U) 445 #define MSCM_CP1CFG3_CMP_SHIFT (3U) 446 #define MSCM_CP1CFG3_CMP_WIDTH (1U) 447 #define MSCM_CP1CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_CMP_SHIFT)) & MSCM_CP1CFG3_CMP_MASK) 448 449 #define MSCM_CP1CFG3_CPY_MASK (0x10U) 450 #define MSCM_CP1CFG3_CPY_SHIFT (4U) 451 #define MSCM_CP1CFG3_CPY_WIDTH (1U) 452 #define MSCM_CP1CFG3_CPY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP1CFG3_CPY_SHIFT)) & MSCM_CP1CFG3_CPY_MASK) 453 /*! @} */ 454 455 /*! @name CP2TYPE - Core Processor 2 Type */ 456 /*! @{ */ 457 458 #define MSCM_CP2TYPE_PERSONALITY_MASK (0xFFFFFFFFU) 459 #define MSCM_CP2TYPE_PERSONALITY_SHIFT (0U) 460 #define MSCM_CP2TYPE_PERSONALITY_WIDTH (32U) 461 #define MSCM_CP2TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2TYPE_PERSONALITY_SHIFT)) & MSCM_CP2TYPE_PERSONALITY_MASK) 462 /*! @} */ 463 464 /*! @name CP2NUM - Core Processor 2 Number */ 465 /*! @{ */ 466 467 #define MSCM_CP2NUM_CPN_MASK (0xFU) 468 #define MSCM_CP2NUM_CPN_SHIFT (0U) 469 #define MSCM_CP2NUM_CPN_WIDTH (4U) 470 #define MSCM_CP2NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2NUM_CPN_SHIFT)) & MSCM_CP2NUM_CPN_MASK) 471 /*! @} */ 472 473 /*! @name CP2REV - Core Processor 2 Revision */ 474 /*! @{ */ 475 476 #define MSCM_CP2REV_RYPZ_MASK (0xFFU) 477 #define MSCM_CP2REV_RYPZ_SHIFT (0U) 478 #define MSCM_CP2REV_RYPZ_WIDTH (8U) 479 #define MSCM_CP2REV_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2REV_RYPZ_SHIFT)) & MSCM_CP2REV_RYPZ_MASK) 480 /*! @} */ 481 482 /*! @name CP2CFG0 - Core Processor 2 Configuration 0 */ 483 /*! @{ */ 484 485 #define MSCM_CP2CFG0_DCWY_MASK (0xFFU) 486 #define MSCM_CP2CFG0_DCWY_SHIFT (0U) 487 #define MSCM_CP2CFG0_DCWY_WIDTH (8U) 488 #define MSCM_CP2CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG0_DCWY_SHIFT)) & MSCM_CP2CFG0_DCWY_MASK) 489 490 #define MSCM_CP2CFG0_DCSZ_MASK (0xFF00U) 491 #define MSCM_CP2CFG0_DCSZ_SHIFT (8U) 492 #define MSCM_CP2CFG0_DCSZ_WIDTH (8U) 493 #define MSCM_CP2CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG0_DCSZ_SHIFT)) & MSCM_CP2CFG0_DCSZ_MASK) 494 495 #define MSCM_CP2CFG0_ICWY_MASK (0xFF0000U) 496 #define MSCM_CP2CFG0_ICWY_SHIFT (16U) 497 #define MSCM_CP2CFG0_ICWY_WIDTH (8U) 498 #define MSCM_CP2CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG0_ICWY_SHIFT)) & MSCM_CP2CFG0_ICWY_MASK) 499 500 #define MSCM_CP2CFG0_ICSZ_MASK (0xFF000000U) 501 #define MSCM_CP2CFG0_ICSZ_SHIFT (24U) 502 #define MSCM_CP2CFG0_ICSZ_WIDTH (8U) 503 #define MSCM_CP2CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG0_ICSZ_SHIFT)) & MSCM_CP2CFG0_ICSZ_MASK) 504 /*! @} */ 505 506 /*! @name CP2CFG1 - Core Processor 2 Configuration 1 */ 507 /*! @{ */ 508 509 #define MSCM_CP2CFG1_L2WY_MASK (0xFF0000U) 510 #define MSCM_CP2CFG1_L2WY_SHIFT (16U) 511 #define MSCM_CP2CFG1_L2WY_WIDTH (8U) 512 #define MSCM_CP2CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG1_L2WY_SHIFT)) & MSCM_CP2CFG1_L2WY_MASK) 513 514 #define MSCM_CP2CFG1_L2SZ_MASK (0xFF000000U) 515 #define MSCM_CP2CFG1_L2SZ_SHIFT (24U) 516 #define MSCM_CP2CFG1_L2SZ_WIDTH (8U) 517 #define MSCM_CP2CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG1_L2SZ_SHIFT)) & MSCM_CP2CFG1_L2SZ_MASK) 518 /*! @} */ 519 520 /*! @name CP2CFG2 - Core Processor 2 Configuration 2 */ 521 /*! @{ */ 522 523 #define MSCM_CP2CFG2_ITCM_MASK (0xFFFFU) 524 #define MSCM_CP2CFG2_ITCM_SHIFT (0U) 525 #define MSCM_CP2CFG2_ITCM_WIDTH (16U) 526 #define MSCM_CP2CFG2_ITCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG2_ITCM_SHIFT)) & MSCM_CP2CFG2_ITCM_MASK) 527 528 #define MSCM_CP2CFG2_TCM_MASK (0xFFFF0000U) 529 #define MSCM_CP2CFG2_TCM_SHIFT (16U) 530 #define MSCM_CP2CFG2_TCM_WIDTH (16U) 531 #define MSCM_CP2CFG2_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG2_TCM_SHIFT)) & MSCM_CP2CFG2_TCM_MASK) 532 /*! @} */ 533 534 /*! @name CP2CFG3 - Core Processor 2 Configuration 3 */ 535 /*! @{ */ 536 537 #define MSCM_CP2CFG3_FPU_MASK (0x1U) 538 #define MSCM_CP2CFG3_FPU_SHIFT (0U) 539 #define MSCM_CP2CFG3_FPU_WIDTH (1U) 540 #define MSCM_CP2CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG3_FPU_SHIFT)) & MSCM_CP2CFG3_FPU_MASK) 541 542 #define MSCM_CP2CFG3_SIMD_MASK (0x2U) 543 #define MSCM_CP2CFG3_SIMD_SHIFT (1U) 544 #define MSCM_CP2CFG3_SIMD_WIDTH (1U) 545 #define MSCM_CP2CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG3_SIMD_SHIFT)) & MSCM_CP2CFG3_SIMD_MASK) 546 547 #define MSCM_CP2CFG3_MMU_MASK (0x4U) 548 #define MSCM_CP2CFG3_MMU_SHIFT (2U) 549 #define MSCM_CP2CFG3_MMU_WIDTH (1U) 550 #define MSCM_CP2CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG3_MMU_SHIFT)) & MSCM_CP2CFG3_MMU_MASK) 551 552 #define MSCM_CP2CFG3_CMP_MASK (0x8U) 553 #define MSCM_CP2CFG3_CMP_SHIFT (3U) 554 #define MSCM_CP2CFG3_CMP_WIDTH (1U) 555 #define MSCM_CP2CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG3_CMP_SHIFT)) & MSCM_CP2CFG3_CMP_MASK) 556 557 #define MSCM_CP2CFG3_CPY_MASK (0x10U) 558 #define MSCM_CP2CFG3_CPY_SHIFT (4U) 559 #define MSCM_CP2CFG3_CPY_WIDTH (1U) 560 #define MSCM_CP2CFG3_CPY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP2CFG3_CPY_SHIFT)) & MSCM_CP2CFG3_CPY_MASK) 561 /*! @} */ 562 563 /*! @name CP3TYPE - Core Processor 3 Type */ 564 /*! @{ */ 565 566 #define MSCM_CP3TYPE_PERSONALITY_MASK (0xFFFFFFFFU) 567 #define MSCM_CP3TYPE_PERSONALITY_SHIFT (0U) 568 #define MSCM_CP3TYPE_PERSONALITY_WIDTH (32U) 569 #define MSCM_CP3TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3TYPE_PERSONALITY_SHIFT)) & MSCM_CP3TYPE_PERSONALITY_MASK) 570 /*! @} */ 571 572 /*! @name CP3NUM - Core Processor 3 Number */ 573 /*! @{ */ 574 575 #define MSCM_CP3NUM_CPN_MASK (0xFU) 576 #define MSCM_CP3NUM_CPN_SHIFT (0U) 577 #define MSCM_CP3NUM_CPN_WIDTH (4U) 578 #define MSCM_CP3NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3NUM_CPN_SHIFT)) & MSCM_CP3NUM_CPN_MASK) 579 /*! @} */ 580 581 /*! @name CP3REV - Core Processor 3 Revision */ 582 /*! @{ */ 583 584 #define MSCM_CP3REV_RYPZ_MASK (0xFFU) 585 #define MSCM_CP3REV_RYPZ_SHIFT (0U) 586 #define MSCM_CP3REV_RYPZ_WIDTH (8U) 587 #define MSCM_CP3REV_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3REV_RYPZ_SHIFT)) & MSCM_CP3REV_RYPZ_MASK) 588 /*! @} */ 589 590 /*! @name CP3CFG0 - Core Processor 3 Configuration 0 */ 591 /*! @{ */ 592 593 #define MSCM_CP3CFG0_DCWY_MASK (0xFFU) 594 #define MSCM_CP3CFG0_DCWY_SHIFT (0U) 595 #define MSCM_CP3CFG0_DCWY_WIDTH (8U) 596 #define MSCM_CP3CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG0_DCWY_SHIFT)) & MSCM_CP3CFG0_DCWY_MASK) 597 598 #define MSCM_CP3CFG0_DCSZ_MASK (0xFF00U) 599 #define MSCM_CP3CFG0_DCSZ_SHIFT (8U) 600 #define MSCM_CP3CFG0_DCSZ_WIDTH (8U) 601 #define MSCM_CP3CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG0_DCSZ_SHIFT)) & MSCM_CP3CFG0_DCSZ_MASK) 602 603 #define MSCM_CP3CFG0_ICWY_MASK (0xFF0000U) 604 #define MSCM_CP3CFG0_ICWY_SHIFT (16U) 605 #define MSCM_CP3CFG0_ICWY_WIDTH (8U) 606 #define MSCM_CP3CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG0_ICWY_SHIFT)) & MSCM_CP3CFG0_ICWY_MASK) 607 608 #define MSCM_CP3CFG0_ICSZ_MASK (0xFF000000U) 609 #define MSCM_CP3CFG0_ICSZ_SHIFT (24U) 610 #define MSCM_CP3CFG0_ICSZ_WIDTH (8U) 611 #define MSCM_CP3CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG0_ICSZ_SHIFT)) & MSCM_CP3CFG0_ICSZ_MASK) 612 /*! @} */ 613 614 /*! @name CP3CFG1 - Core Processor 3 Configuration 1 */ 615 /*! @{ */ 616 617 #define MSCM_CP3CFG1_L2WY_MASK (0xFF0000U) 618 #define MSCM_CP3CFG1_L2WY_SHIFT (16U) 619 #define MSCM_CP3CFG1_L2WY_WIDTH (8U) 620 #define MSCM_CP3CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG1_L2WY_SHIFT)) & MSCM_CP3CFG1_L2WY_MASK) 621 622 #define MSCM_CP3CFG1_L2SZ_MASK (0xFF000000U) 623 #define MSCM_CP3CFG1_L2SZ_SHIFT (24U) 624 #define MSCM_CP3CFG1_L2SZ_WIDTH (8U) 625 #define MSCM_CP3CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG1_L2SZ_SHIFT)) & MSCM_CP3CFG1_L2SZ_MASK) 626 /*! @} */ 627 628 /*! @name CP3CFG2 - Core Processor 3 Configuration 2 */ 629 /*! @{ */ 630 631 #define MSCM_CP3CFG2_ITCM_MASK (0xFFFFU) 632 #define MSCM_CP3CFG2_ITCM_SHIFT (0U) 633 #define MSCM_CP3CFG2_ITCM_WIDTH (16U) 634 #define MSCM_CP3CFG2_ITCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG2_ITCM_SHIFT)) & MSCM_CP3CFG2_ITCM_MASK) 635 636 #define MSCM_CP3CFG2_TCM_MASK (0xFFFF0000U) 637 #define MSCM_CP3CFG2_TCM_SHIFT (16U) 638 #define MSCM_CP3CFG2_TCM_WIDTH (16U) 639 #define MSCM_CP3CFG2_TCM(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG2_TCM_SHIFT)) & MSCM_CP3CFG2_TCM_MASK) 640 /*! @} */ 641 642 /*! @name CP3CFG3 - Core Processor 3 Configuration 3 */ 643 /*! @{ */ 644 645 #define MSCM_CP3CFG3_FPU_MASK (0x1U) 646 #define MSCM_CP3CFG3_FPU_SHIFT (0U) 647 #define MSCM_CP3CFG3_FPU_WIDTH (1U) 648 #define MSCM_CP3CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG3_FPU_SHIFT)) & MSCM_CP3CFG3_FPU_MASK) 649 650 #define MSCM_CP3CFG3_SIMD_MASK (0x2U) 651 #define MSCM_CP3CFG3_SIMD_SHIFT (1U) 652 #define MSCM_CP3CFG3_SIMD_WIDTH (1U) 653 #define MSCM_CP3CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG3_SIMD_SHIFT)) & MSCM_CP3CFG3_SIMD_MASK) 654 655 #define MSCM_CP3CFG3_MMU_MASK (0x4U) 656 #define MSCM_CP3CFG3_MMU_SHIFT (2U) 657 #define MSCM_CP3CFG3_MMU_WIDTH (1U) 658 #define MSCM_CP3CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG3_MMU_SHIFT)) & MSCM_CP3CFG3_MMU_MASK) 659 660 #define MSCM_CP3CFG3_CMP_MASK (0x8U) 661 #define MSCM_CP3CFG3_CMP_SHIFT (3U) 662 #define MSCM_CP3CFG3_CMP_WIDTH (1U) 663 #define MSCM_CP3CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG3_CMP_SHIFT)) & MSCM_CP3CFG3_CMP_MASK) 664 665 #define MSCM_CP3CFG3_CPY_MASK (0x10U) 666 #define MSCM_CP3CFG3_CPY_SHIFT (4U) 667 #define MSCM_CP3CFG3_CPY_WIDTH (1U) 668 #define MSCM_CP3CFG3_CPY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP3CFG3_CPY_SHIFT)) & MSCM_CP3CFG3_CPY_MASK) 669 /*! @} */ 670 671 /*! @name IRSPRC - Interrupt Router Shared Peripheral Routing Control */ 672 /*! @{ */ 673 674 #define MSCM_IRSPRC_RTU0_GIC_MASK (0x1U) 675 #define MSCM_IRSPRC_RTU0_GIC_SHIFT (0U) 676 #define MSCM_IRSPRC_RTU0_GIC_WIDTH (1U) 677 #define MSCM_IRSPRC_RTU0_GIC(x) (((uint16_t)(((uint16_t)(x)) << MSCM_IRSPRC_RTU0_GIC_SHIFT)) & MSCM_IRSPRC_RTU0_GIC_MASK) 678 679 #define MSCM_IRSPRC_RTU1_GIC_MASK (0x2U) 680 #define MSCM_IRSPRC_RTU1_GIC_SHIFT (1U) 681 #define MSCM_IRSPRC_RTU1_GIC_WIDTH (1U) 682 #define MSCM_IRSPRC_RTU1_GIC(x) (((uint16_t)(((uint16_t)(x)) << MSCM_IRSPRC_RTU1_GIC_SHIFT)) & MSCM_IRSPRC_RTU1_GIC_MASK) 683 684 #define MSCM_IRSPRC_SMU_CORE_MASK (0x4U) 685 #define MSCM_IRSPRC_SMU_CORE_SHIFT (2U) 686 #define MSCM_IRSPRC_SMU_CORE_WIDTH (1U) 687 #define MSCM_IRSPRC_SMU_CORE(x) (((uint16_t)(((uint16_t)(x)) << MSCM_IRSPRC_SMU_CORE_SHIFT)) & MSCM_IRSPRC_SMU_CORE_MASK) 688 689 #define MSCM_IRSPRC_LOCK_MASK (0x8000U) 690 #define MSCM_IRSPRC_LOCK_SHIFT (15U) 691 #define MSCM_IRSPRC_LOCK_WIDTH (1U) 692 #define MSCM_IRSPRC_LOCK(x) (((uint16_t)(((uint16_t)(x)) << MSCM_IRSPRC_LOCK_SHIFT)) & MSCM_IRSPRC_LOCK_MASK) 693 /*! @} */ 694 695 /*! 696 * @} 697 */ /* end of group MSCM_Register_Masks */ 698 699 /*! 700 * @} 701 */ /* end of group MSCM_Peripheral_Access_Layer */ 702 703 #endif /* #if !defined(S32Z2_MSCM_H_) */ 704
