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Searched refs:MSCM_CP0CFG3_SIMD_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DS32K118_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DS32K148_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DS32K142W_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DS32K142_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DS32K146_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DS32K144W_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DS32K144_MSCM.h356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
359 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MSCM.h331 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
334 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MSCM.h335 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
338 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h25235 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
25241 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h27404 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
27410 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h28618 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
28624 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)
DMCXW727C_cm33_core1.h36370 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) macro
36376 … (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK)