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Searched refs:MRCC_MRCC_LPSPI1_DIV_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h24188 #define MRCC_MRCC_LPSPI1_DIV_MASK (0xF00U) macro
24191 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h26357 #define MRCC_MRCC_LPSPI1_DIV_MASK (0xF00U) macro
26360 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h27296 #define MRCC_MRCC_LPSPI1_DIV_MASK (0xF00U) macro
27299 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_DIV_MASK)
DMCXW727C_cm33_core1.h35048 #define MRCC_MRCC_LPSPI1_DIV_MASK (0xF00U) macro
35051 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_DIV_MASK)