Searched refs:MRCC_MRCC_LPADC0_DIV_MASK (Results 1 – 4 of 4) sorted by relevance
24564 #define MRCC_MRCC_LPADC0_DIV_MASK (0xF00U) macro24567 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_DIV_SHIFT)) & MRCC_MRCC_LPADC0_DIV_MASK)
26733 #define MRCC_MRCC_LPADC0_DIV_MASK (0xF00U) macro26736 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_DIV_SHIFT)) & MRCC_MRCC_LPADC0_DIV_MASK)
27687 #define MRCC_MRCC_LPADC0_DIV_MASK (0xF00U) macro27690 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_DIV_SHIFT)) & MRCC_MRCC_LPADC0_DIV_MASK)
35439 #define MRCC_MRCC_LPADC0_DIV_MASK (0xF00U) macro35442 … (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPADC0_DIV_SHIFT)) & MRCC_MRCC_LPADC0_DIV_MASK)
