Searched refs:MRCC_DIV_MASK (Results 1 – 10 of 10) sorted by relevance
187 freq = CLOCK_GetSircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()190 freq = CLOCK_GetFircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()193 freq = CLOCK_GetSysOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()207 freq = CLOCK_GetSircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()210 freq = CLOCK_GetFircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()213 freq = CLOCK_GetSysOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()216 freq = CLOCK_GetRtcOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()228 freq = CLOCK_GetFircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()231 freq = CLOCK_GetSysOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()
768 reg = (reg & (~MRCC_DIV_MASK)) | MRCC_DIV(divValue); in CLOCK_SetIpSrcDiv()
187 freq = CLOCK_GetSircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()190 freq = CLOCK_GetFircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()193 freq = CLOCK_GetSysOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()207 freq = CLOCK_GetSircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()210 freq = CLOCK_GetFircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()213 freq = CLOCK_GetSysOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()216 freq = CLOCK_GetRtcOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()227 freq = CLOCK_GetFircFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()230 freq = CLOCK_GetSysOscFreq() / (((reg & MRCC_DIV_MASK) >> MRCC_DIV_SHIFT) + 1U); in CLOCK_GetIpFreq()
706 reg = (reg & (~MRCC_DIV_MASK)) | MRCC_DIV(divValue); in CLOCK_SetIpSrcDiv()
24907 #define MRCC_DIV_MASK (0xF00U) macro24909 …x) (((uint32_t)(((uint32_t)(x)) << MRCC_DIV_SHIFT)) & MRCC_DIV_MASK)
27076 #define MRCC_DIV_MASK (0xF00U) macro27078 …x) (((uint32_t)(((uint32_t)(x)) << MRCC_DIV_SHIFT)) & MRCC_DIV_MASK)
28289 #define MRCC_DIV_MASK (0xF00U) macro28291 …x) (((uint32_t)(((uint32_t)(x)) << MRCC_DIV_SHIFT)) & MRCC_DIV_MASK)
36041 #define MRCC_DIV_MASK (0xF00U) macro36043 …x) (((uint32_t)(((uint32_t)(x)) << MRCC_DIV_SHIFT)) & MRCC_DIV_MASK)
