| /hal_nxp-latest/mcux/mcux-sdk/drivers/rdc/ |
| D | fsl_rdc.h | 359 base->MR[mem].MRC |= RDC_MRC_LCK_MASK; in RDC_LockMemAccessConfig()
376 base->MR[mem].MRC |= RDC_MRC_ENA_MASK; in RDC_SetMemAccessValid()
380 base->MR[mem].MRC &= ~RDC_MRC_ENA_MASK; in RDC_SetMemAccessValid()
424 return (uint8_t)((base->MR[mem].MRC >> (domainId * 2U)) & 0x03U); in RDC_GetMemAccessPolicy()
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| D | fsl_rdc.c | 248 base->MR[mem].MRC = regMRC; in RDC_SetMemAccessConfig()
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| /hal_nxp-latest/imx/drivers/ |
| D | rdc.c | 48 base->MR[mr].MRC = perm | (enable ? RDC_MRC_ENA_MASK : 0) | (lock ? RDC_MRC_LCK_MASK : 0); in RDC_SetMrAccess()
64 return base->MR[mr].MRC & 0xFF; in RDC_GetMrAccess()
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| D | rdc.h | 232 return (bool)(base->MR[mr].MRC & RDC_MRC_ENA_MASK); in RDC_IsMrEnabled()
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| /hal_nxp-latest/s32/drivers/s32k3/Fls/src/ |
| D | Qspi_Ip_Controller.c | 1926 BaseAddr->MRC = 0x00500E07UL; in Qspi_Ip_ResetPrivilegedRegisters_Privileged()
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/ |
| D | Qspi_Ip_Controller.c | 2264 BaseAddr->MRC = 0x00000E07UL; in Qspi_Ip_ResetPrivilegedRegisters_Privileged()
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_QUADSPI.h | 153 __IO uint32_t MRC; /**< Master Read Command, offset: 0x924 */ member
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 31122 …__IO uint32_t MRC; /**< Memory Region Control, array offset:… member
31145 #define RDC_MRC_REG(base,index) ((base)->MR[index].MRC)
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| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 38317 …__IO uint32_t MRC; /**< Memory Region Control, array offset:… member
38340 #define RDC_MRC_REG(base,index) ((base)->MR[index].MRC)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 43675 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 43673 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 43673 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/ |
| D | MIMXRT735S_hifi1.h | 63590 __IO uint32_t MRC; /**< Manager Read Command, offset: 0x924 */ member
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| D | MIMXRT735S_cm33_core1.h | 63659 __IO uint32_t MRC; /**< Manager Read Command, offset: 0x924 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 43675 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 43675 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_cm7.h | 43673 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| D | MIMX8MN6_ca53.h | 43687 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 44761 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/ |
| D | MIMXRT758S_cm33_core1.h | 66882 __IO uint32_t MRC; /**< Manager Read Command, offset: 0x924 */ member
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| D | MIMXRT758S_hifi1.h | 66811 __IO uint32_t MRC; /**< Manager Read Command, offset: 0x924 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 46934 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 46934 …__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, … member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/ |
| D | MIMXRT798S_hifi1.h | 66811 __IO uint32_t MRC; /**< Manager Read Command, offset: 0x924 */ member
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| D | MIMXRT798S_cm33_core1.h | 66882 __IO uint32_t MRC; /**< Manager Read Command, offset: 0x924 */ member
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