| /hal_nxp-latest/imx/drivers/ |
| D | rdc.c | 46 base->MR[mr].MRSA = startAddr; in RDC_SetMrAccess()
47 base->MR[mr].MREA = endAddr; in RDC_SetMrAccess()
48 base->MR[mr].MRC = perm | (enable ? RDC_MRC_ENA_MASK : 0) | (lock ? RDC_MRC_LCK_MASK : 0); in RDC_SetMrAccess()
60 *startAddr = base->MR[mr].MRSA; in RDC_GetMrAccess()
62 *endAddr = base->MR[mr].MREA; in RDC_GetMrAccess()
64 return base->MR[mr].MRC & 0xFF; in RDC_GetMrAccess()
77 mrvs = base->MR[mr].MRVS; in RDC_GetViolationStatus()
|
| D | rdc.h | 232 return (bool)(base->MR[mr].MRC & RDC_MRC_ENA_MASK); in RDC_IsMrEnabled()
256 base->MR[mr].MRVS = RDC_MRVS_AD_MASK; in RDC_ClearViolationStatus()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/rdc/ |
| D | fsl_rdc.c | 242 …base->MR[mem].MRSA = (uint32_t)(config->baseAddress >> (uint32_t)FSL_FEATURE_RDC_MEM_REGION_ADDR_S… in RDC_SetMemAccessConfig()
243 …base->MR[mem].MREA = (uint32_t)(config->endAddress >> (uint32_t)FSL_FEATURE_RDC_MEM_REGION_ADDR_SH… in RDC_SetMemAccessConfig()
245 base->MR[mem].MRSA = (uint32_t)config->baseAddress; in RDC_SetMemAccessConfig()
246 base->MR[mem].MREA = (uint32_t)config->endAddress; in RDC_SetMemAccessConfig()
248 base->MR[mem].MRC = regMRC; in RDC_SetMemAccessConfig()
299 uint32_t regMRVS = base->MR[mem].MRVS; in RDC_GetMemViolationStatus()
|
| D | fsl_rdc.h | 359 base->MR[mem].MRC |= RDC_MRC_LCK_MASK; in RDC_LockMemAccessConfig()
376 base->MR[mem].MRC |= RDC_MRC_ENA_MASK; in RDC_SetMemAccessValid()
380 base->MR[mem].MRC &= ~RDC_MRC_ENA_MASK; in RDC_SetMemAccessValid()
409 base->MR[mem].MRVS = RDC_MRVS_AD_MASK; in RDC_ClearMemViolationFlag()
424 return (uint8_t)((base->MR[mem].MRC >> (domainId * 2U)) & 0x03U); in RDC_GetMemAccessPolicy()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/ctimer/ |
| D | fsl_ctimer.c | 244 base->MR[pwmPeriodChannel] = period; in CTIMER_SetupPwm()
247 base->MR[matchChannel] = pulsePeriod; in CTIMER_SetupPwm()
321 base->MR[pwmPeriodChannel] = pwmPeriod; in CTIMER_SetupPwmPeriod()
324 base->MR[matchChannel] = pulsePeriod; in CTIMER_SetupPwmPeriod()
355 period = base->MR[pwmPeriodChannel]; in CTIMER_UpdatePwmDutycycle()
368 base->MR[matchChannel] = pulsePeriod; in CTIMER_UpdatePwmDutycycle()
410 base->MR[matchChannel] = config->matchValue; in CTIMER_SetupMatch()
|
| D | fsl_ctimer.h | 286 base->MR[matchChannel] = pulsePeriod; in CTIMER_UpdatePwmPulsePeriod()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/rcm/ |
| D | fsl_rcm.h | 341 return (bool)(base->MR & RCM_MR_EZP_MS_MASK); in RCM_GetEasyPortModePinStatus()
356 … return (rcm_boot_rom_config_t)(uint8_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); in RCM_GetBootRomSource()
368 base->MR |= RCM_MR_BOOTROM_MASK; in RCM_ClearBootRomSource()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/rtd_cmc/ |
| D | fsl_rtd_cmc.h | 540 return (uint8_t)((base->MR[0] & CMC_MR_BOOTCFG_MASK) >> CMC_MR_BOOTCFG_SHIFT);
550 base->MR[0] = CMC_MR_BOOTCFG_MASK;
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_cmc/ |
| D | fsl_cmc.h | 638 return (uint8_t)((base->MR[0] & CMC_MR_ISPMODE_n_MASK) >> CMC_MR_ISPMODE_n_SHIFT); in CMC_GetISPMODEPinLogic()
648 base->MR[0] = CMC_MR_ISPMODE_n_MASK; in CMC_ClearISPMODEPinLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/cmc/ |
| D | fsl_cmc.h | 620 return (uint8_t)((base->MR[0] & CMC_MR_ISPMODE_n_MASK) >> CMC_MR_ISPMODE_n_SHIFT); in CMC_GetISPMODEPinLogic()
630 base->MR[0] = CMC_MR_ISPMODE_n_MASK; in CMC_ClearISPMODEPinLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/ |
| D | system_MKE15Z7.c | 78 RCM->MR = 3UL << 1U; in SystemInit()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/ |
| D | system_MKE14Z7.c | 78 RCM->MR = 3UL << 1U; in SystemInit()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/msmc/ |
| D | fsl_msmc.h | 658 return base->MR; in SMC_GetBootOptionConfig()
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/ |
| D | fsl_smartcard_usim.c | 399 CTIMER0->MR[0] = time; in SMARTCARD_USIM_TimerStart()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/ |
| D | MCXC041.h | 4619 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC802/ |
| D | LPC802.h | 1175 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC804/ |
| D | LPC804.h | 1557 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/ |
| D | MKL17Z644.h | 5990 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/ |
| D | MCXC141.h | 6732 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/ |
| D | MCXC142.h | 6730 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC844/ |
| D | LPC844.h | 1255 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC845/ |
| D | LPC845.h | 1661 …__IO uint32_t MR[4]; /**< Match Register . MR can be enabled through t… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/ |
| D | MCXC242.h | 6732 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/ |
| D | MKL27Z644.h | 5999 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/ |
| D | MCXC144.h | 7375 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ member
|
