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Searched refs:MPZQHWCTRL (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h26162 …__IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offse… member
26253 #define MMDC_MPZQHWCTRL_REG(base) ((base)->MPZQHWCTRL)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h18298 …__IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x8… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h18299 …__IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x8… member