Searched refs:MPU_RASR_SIZE_Pos (Results 1 – 15 of 15) sorted by relevance
73 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()96 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()108 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()137 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()
76 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()99 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()111 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()140 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()
105 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()134 (30 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()163 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()
162 (0x3 << MPU_RASR_SRD_Pos) | (28 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()191 (30 << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()220 (0x1 << MPU_RASR_B_Pos) | ((i - 1) << MPU_RASR_SIZE_Pos) | MPU_RASR_ENABLE_Msk; in BOARD_InitMemory()
603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
108 … (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
1209 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro1210 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
1226 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro1227 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
1284 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro1285 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
1507 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro1508 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
1289 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro1290 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
1516 #define MPU_RASR_SIZE_Pos 1U /*!< MPU … macro1517 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU …
