Home
last modified time | relevance | path

Searched refs:MPU_RASR_AP_Pos (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8mm/
Dboard.c72 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | in BOARD_InitMemory()
96 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()
108 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()
136 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | in BOARD_InitMemory()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8mq/
Dboard.c75 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | in BOARD_InitMemory()
99 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()
111 …MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (29 << MPU_RASR_SIZE_Pos) | MPU_R… in BOARD_InitMemory()
139 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | in BOARD_InitMemory()
/hal_nxp-latest/mcux/mcux-sdk/boards/mekmimx8qm/
Dboard.c104 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | in BOARD_InitMemory()
133 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (0xC0 << MPU_RASR_SRD_Pos) | in BOARD_InitMemory()
162 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | in BOARD_InitMemory()
/hal_nxp-latest/mcux/mcux-sdk/boards/mekmimx8qx/
Dboard.c161 MPU->RASR = (0x1 << MPU_RASR_XN_Pos) | (0x3 << MPU_RASR_AP_Pos) | (0x2 << MPU_RASR_TEX_Pos) | in BOARD_InitMemory()
190 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_B_Pos) | (0xC0 << MPU_RASR_SRD_Pos) | in BOARD_InitMemory()
219 MPU->RASR = (0x3 << MPU_RASR_AP_Pos) | (0x1 << MPU_RASR_TEX_Pos) | (0x1 << MPU_RASR_C_Pos) | in BOARD_InitMemory()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcore_sc000.h585 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
Dcore_cm0plus.h576 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
Dmpu_armv7.h105 … (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
Dcore_sc300.h1191 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
1192 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
Dcore_cm3.h1208 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
1209 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
Dcore_cm4.h1266 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
1267 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
Dcore_cm7.h1489 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
1490 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcore_cm0plus.h576 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
Dmpu_armv7.h105 … (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
Dcore_cm4.h1271 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
1272 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …
Dcore_cm7.h1498 #define MPU_RASR_AP_Pos 24U /*!< MPU … macro
1499 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU …