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Searched refs:MPIDR_AFFLVL_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/
Dcore_common.h72 #define MPIDR_AFFLVL_MASK (0xffULL) macro
84 (((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
87 ((MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
88 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
89 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
90 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
Dgic_v3.h238 aff = (aff0 & MPIDR_AFFLVL_MASK) << 0 | in GIC_MPIDRtoAffinity()
239 (aff1 & MPIDR_AFFLVL_MASK) << 8 | in GIC_MPIDRtoAffinity()
240 (aff2 & MPIDR_AFFLVL_MASK) << 16 | in GIC_MPIDRtoAffinity()
241 (aff3 & MPIDR_AFFLVL_MASK) << 24; in GIC_MPIDRtoAffinity()
Dcmsis_gcc.h141 (mpidr >> (8 * MPIDR_SUPPORT_MT(mpidr))) & MPIDR_AFFLVL_MASK; })