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Searched refs:MMU_CTRL_INV_ADDR_MODE_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h31796 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
31802 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT735S_cm33_core1.h31840 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
31846 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT735S_ezhv.h45494 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
45500 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT735S_cm33_core0.h46330 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
46336 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h34637 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
34643 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT758S_hifi1.h34591 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
34597 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT758S_cm33_core0.h49129 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
49135 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT758S_ezhv.h48232 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
48238 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h34591 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
34597 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT798S_cm33_core1.h34637 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
34643 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT798S_hifi4.h49060 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
49066 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT798S_cm33_core0.h49129 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
49135 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)
DMIMXRT798S_ezhv.h48232 #define MMU_CTRL_INV_ADDR_MODE_MASK (0x10U) macro
48238 … (((uint32_t)(((uint32_t)(x)) << MMU_CTRL_INV_ADDR_MODE_SHIFT)) & MMU_CTRL_INV_ADDR_MODE_MASK)