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Searched refs:MMU2_BASE (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h32071 #define MMU2_BASE (0x500A8000u) macro
32075 #define MMU2 ((MMU_Type *)MMU2_BASE)
32079 #define MMU_BASE_ADDRS { MMU2_BASE }
32088 #define MMU2_BASE (0x400A8000u) macro
32090 #define MMU2 ((MMU_Type *)MMU2_BASE)
32092 #define MMU_BASE_ADDRS { MMU2_BASE }
DMIMXRT735S_cm33_core1.h32115 #define MMU2_BASE (0x500A8000u) macro
32119 #define MMU2 ((MMU_Type *)MMU2_BASE)
32123 #define MMU_BASE_ADDRS { MMU2_BASE }
32132 #define MMU2_BASE (0x400A8000u) macro
32134 #define MMU2 ((MMU_Type *)MMU2_BASE)
32136 #define MMU_BASE_ADDRS { MMU2_BASE }
DMIMXRT735S_cm33_core0.h46621 #define MMU2_BASE (0x500A8000u) macro
46625 #define MMU2 ((MMU_Type *)MMU2_BASE)
46629 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
46646 #define MMU2_BASE (0x400A8000u) macro
46648 #define MMU2 ((MMU_Type *)MMU2_BASE)
46650 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT735S_ezhv.h45776 #define MMU2_BASE (0x400A8000u) macro
45778 #define MMU2 ((MMU_Type *)MMU2_BASE)
45780 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h34912 #define MMU2_BASE (0x500A8000u) macro
34916 #define MMU2 ((MMU_Type *)MMU2_BASE)
34920 #define MMU_BASE_ADDRS { MMU2_BASE }
34929 #define MMU2_BASE (0x400A8000u) macro
34931 #define MMU2 ((MMU_Type *)MMU2_BASE)
34933 #define MMU_BASE_ADDRS { MMU2_BASE }
DMIMXRT758S_hifi1.h34866 #define MMU2_BASE (0x500A8000u) macro
34870 #define MMU2 ((MMU_Type *)MMU2_BASE)
34874 #define MMU_BASE_ADDRS { MMU2_BASE }
34883 #define MMU2_BASE (0x400A8000u) macro
34885 #define MMU2 ((MMU_Type *)MMU2_BASE)
34887 #define MMU_BASE_ADDRS { MMU2_BASE }
DMIMXRT758S_cm33_core0.h49420 #define MMU2_BASE (0x500A8000u) macro
49424 #define MMU2 ((MMU_Type *)MMU2_BASE)
49428 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49445 #define MMU2_BASE (0x400A8000u) macro
49447 #define MMU2 ((MMU_Type *)MMU2_BASE)
49449 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT758S_ezhv.h48514 #define MMU2_BASE (0x400A8000u) macro
48516 #define MMU2 ((MMU_Type *)MMU2_BASE)
48518 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h34866 #define MMU2_BASE (0x500A8000u) macro
34870 #define MMU2 ((MMU_Type *)MMU2_BASE)
34874 #define MMU_BASE_ADDRS { MMU2_BASE }
34883 #define MMU2_BASE (0x400A8000u) macro
34885 #define MMU2 ((MMU_Type *)MMU2_BASE)
34887 #define MMU_BASE_ADDRS { MMU2_BASE }
DMIMXRT798S_cm33_core1.h34912 #define MMU2_BASE (0x500A8000u) macro
34916 #define MMU2 ((MMU_Type *)MMU2_BASE)
34920 #define MMU_BASE_ADDRS { MMU2_BASE }
34929 #define MMU2_BASE (0x400A8000u) macro
34931 #define MMU2 ((MMU_Type *)MMU2_BASE)
34933 #define MMU_BASE_ADDRS { MMU2_BASE }
DMIMXRT798S_hifi4.h49351 #define MMU2_BASE (0x500A8000u) macro
49355 #define MMU2 ((MMU_Type *)MMU2_BASE)
49359 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49376 #define MMU2_BASE (0x400A8000u) macro
49378 #define MMU2 ((MMU_Type *)MMU2_BASE)
49380 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT798S_cm33_core0.h49420 #define MMU2_BASE (0x500A8000u) macro
49424 #define MMU2 ((MMU_Type *)MMU2_BASE)
49428 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49445 #define MMU2_BASE (0x400A8000u) macro
49447 #define MMU2 ((MMU_Type *)MMU2_BASE)
49449 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT798S_ezhv.h48514 #define MMU2_BASE (0x400A8000u) macro
48516 #define MMU2 ((MMU_Type *)MMU2_BASE)
48518 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }