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Searched refs:MMU1_BASE (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h49343 #define MMU1_BASE (0x50031000u) macro
49347 #define MMU1 ((MMU_Type *)MMU1_BASE)
49359 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49372 #define MMU1_BASE (0x40031000u) macro
49374 #define MMU1 ((MMU_Type *)MMU1_BASE)
49380 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT798S_cm33_core0.h49412 #define MMU1_BASE (0x50031000u) macro
49416 #define MMU1 ((MMU_Type *)MMU1_BASE)
49428 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49441 #define MMU1_BASE (0x40031000u) macro
49443 #define MMU1 ((MMU_Type *)MMU1_BASE)
49449 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT798S_ezhv.h48510 #define MMU1_BASE (0x40031000u) macro
48512 #define MMU1 ((MMU_Type *)MMU1_BASE)
48518 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h46613 #define MMU1_BASE (0x50031000u) macro
46617 #define MMU1 ((MMU_Type *)MMU1_BASE)
46629 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
46642 #define MMU1_BASE (0x40031000u) macro
46644 #define MMU1 ((MMU_Type *)MMU1_BASE)
46650 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT735S_ezhv.h45772 #define MMU1_BASE (0x40031000u) macro
45774 #define MMU1 ((MMU_Type *)MMU1_BASE)
45780 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h49412 #define MMU1_BASE (0x50031000u) macro
49416 #define MMU1 ((MMU_Type *)MMU1_BASE)
49428 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49441 #define MMU1_BASE (0x40031000u) macro
49443 #define MMU1 ((MMU_Type *)MMU1_BASE)
49449 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT758S_ezhv.h48510 #define MMU1_BASE (0x40031000u) macro
48512 #define MMU1 ((MMU_Type *)MMU1_BASE)
48518 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }