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Searched refs:MMU0_BASE (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h49335 #define MMU0_BASE (0x50030000u) macro
49339 #define MMU0 ((MMU_Type *)MMU0_BASE)
49359 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49368 #define MMU0_BASE (0x40030000u) macro
49370 #define MMU0 ((MMU_Type *)MMU0_BASE)
49380 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT798S_cm33_core0.h49404 #define MMU0_BASE (0x50030000u) macro
49408 #define MMU0 ((MMU_Type *)MMU0_BASE)
49428 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49437 #define MMU0_BASE (0x40030000u) macro
49439 #define MMU0 ((MMU_Type *)MMU0_BASE)
49449 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT798S_ezhv.h48506 #define MMU0_BASE (0x40030000u) macro
48508 #define MMU0 ((MMU_Type *)MMU0_BASE)
48518 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h46605 #define MMU0_BASE (0x50030000u) macro
46609 #define MMU0 ((MMU_Type *)MMU0_BASE)
46629 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
46638 #define MMU0_BASE (0x40030000u) macro
46640 #define MMU0 ((MMU_Type *)MMU0_BASE)
46650 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT735S_ezhv.h45768 #define MMU0_BASE (0x40030000u) macro
45770 #define MMU0 ((MMU_Type *)MMU0_BASE)
45780 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h49404 #define MMU0_BASE (0x50030000u) macro
49408 #define MMU0 ((MMU_Type *)MMU0_BASE)
49428 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
49437 #define MMU0_BASE (0x40030000u) macro
49439 #define MMU0 ((MMU_Type *)MMU0_BASE)
49449 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }
DMIMXRT758S_ezhv.h48506 #define MMU0_BASE (0x40030000u) macro
48508 #define MMU0 ((MMU_Type *)MMU0_BASE)
48518 #define MMU_BASE_ADDRS { MMU0_BASE, MMU1_BASE, MMU2_BASE }