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Searched refs:MMFR (Results 1 – 25 of 92) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/enet/
Dfsl_enet.h983 return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); in ENET_ReadSMIData()
1002 …base->MMFR = ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(reg… in ENET_StartSMIWrite()
1020 base->MMFR = in ENET_StartSMIRead()
1063 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(portAddr) | in ENET_StartExtC45SMIWriteReg()
1081 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(portAddr) | in ENET_StartExtC45SMIWriteData()
1098 base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(portAddr) | in ENET_StartExtC45SMIReadData()
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcore_cm3.h393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ member
Dcore_sc300.h393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ member
Dcore_cm4.h459 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ member
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcore_cm4.h464 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ member
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_ENET.h85 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h9707 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h9720 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/
DMKV58F24.h11962 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h8454 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset:… member
8595 #define ENET_MMFR_REG(base) ((base)->MMFR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/
DMK66F18.h11349 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h11349 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h13096 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset:… member
13237 #define ENET_MMFR_REG(base) ((base)->MMFR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h16532 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h16512 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h18633 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h17562 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h18635 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h18347 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h19001 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h24652 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h24650 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h24650 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h19787 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h19865 …__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 … member

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