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Searched refs:MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h19684 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (0xF80U) macro
19690 …t32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h19685 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (0xF80U) macro
19691 …t32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h26745 #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK 0xF80u macro
26747 …(uint32_t)(((uint32_t)(x))<<MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT))&MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK)