1 /** @file mlan_decl.h 2 * 3 * @brief This file declares the generic data structures and APIs. 4 * 5 * Copyright 2008-2024 NXP 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 * 9 */ 10 11 /****************************************************** 12 Change log: 13 11/07/2008: initial version 14 ******************************************************/ 15 16 #ifndef _MLAN_DECL_H_ 17 #define _MLAN_DECL_H_ 18 19 #include "type_decls.h" 20 #include <osa.h> 21 #if CONFIG_WPA_SUPP 22 #include <ieee802_11_defs.h> 23 #endif 24 25 /** MLAN release version */ 26 #define MLAN_RELEASE_VERSION "310" 27 28 /** Constants below */ 29 30 #ifdef __GNUC__ 31 /** Structure packing begins */ 32 #define MLAN_PACK_START 33 /** Structure packeing end */ 34 #define MLAN_PACK_END __attribute__((packed)) 35 #else /* !__GNUC__ */ 36 #ifdef PRAGMA_PACK 37 /** Structure packing begins */ 38 #define MLAN_PACK_START 39 /** Structure packeing end */ 40 #define MLAN_PACK_END 41 #else /* !PRAGMA_PACK */ 42 /** Structure packing begins */ 43 #define MLAN_PACK_START __packed 44 /** Structure packing end */ 45 #define MLAN_PACK_END 46 #endif /* PRAGMA_PACK */ 47 #endif /* __GNUC__ */ 48 49 #ifndef INLINE 50 #ifdef __GNUC__ 51 /** inline directive */ 52 #define INLINE inline 53 #else 54 /** inline directive */ 55 #define INLINE __inline 56 #endif 57 #endif 58 59 /** MLAN TRUE */ 60 #define MTRUE (1) 61 /** MLAN FALSE */ 62 #define MFALSE (0) 63 64 /** Macros for Data Alignment : size */ 65 #define ALIGN_SZ(p, a) (((p) + ((a)-1U)) & ~((a)-1U)) 66 67 /** Macros for Data Alignment : address */ 68 #define ALIGN_ADDR(p, a) ((((t_ptr)(p)) + (((t_ptr)(a)) - 1U)) & ~(((t_ptr)(a)) - 1U)) 69 70 #ifndef MACSTR 71 /** MAC address security format */ 72 #define MACSTR "%02x:XX:XX:XX:%02x:%02x" 73 #endif 74 75 #ifndef MAC2STR 76 /** MAC address security print arguments */ 77 #define MAC2STR(a) (a)[0], (a)[4], (a)[5] 78 #endif 79 80 /** Return the byte offset of a field in the given structure */ 81 #define MLAN_FIELD_OFFSET(type, field) ((t_u32)(t_ptr) & (((type *)0)->field)) 82 /** Return aligned offset */ 83 #define OFFSET_ALIGN_ADDR(p, a) (t_u32)(ALIGN_ADDR(p, a) - (t_ptr)p) 84 85 /** Maximum BSS numbers */ 86 /* fixme: We have reduced this from 16 to 2. Ensure that this is Ok */ 87 #define MLAN_MAX_BSS_NUM 2U 88 89 /** NET IP alignment */ 90 #define MLAN_NET_IP_ALIGN 0 91 92 /** DMA alignment */ 93 #define DMA_ALIGNMENT 32U 94 /** max size of TxPD */ 95 #define MAX_TXPD_SIZE 32 96 97 /** Minimum data header length */ 98 #define MLAN_MIN_DATA_HEADER_LEN (DMA_ALIGNMENT + MAX_TXPD_SIZE) 99 100 /** rx data header length */ 101 #define MLAN_RX_HEADER_LEN MLAN_MIN_DATA_HEADER_LEN 102 103 /** This is current limit on Maximum Tx AMPDU allowed */ 104 #define MLAN_MAX_TX_BASTREAM_SUPPORTED 2U 105 /** This is current limit on Maximum Rx AMPDU allowed */ 106 #define MLAN_MAX_RX_BASTREAM_SUPPORTED 16 107 108 /** US country code */ 109 #define COUNTRY_CODE_US 0x10 110 111 #ifdef STA_SUPPORT 112 /** Default Win size attached during ADDBA request */ 113 #ifndef MLAN_STA_AMPDU_DEF_TXWINSIZE 114 #if defined(SD9177) && defined(COEX_APP_SUPPORT) 115 #define MLAN_STA_AMPDU_DEF_TXWINSIZE 32 116 #else 117 #define MLAN_STA_AMPDU_DEF_TXWINSIZE 64 118 #endif 119 #endif 120 121 /** Default Win size attached during ADDBA response */ 122 #ifndef MLAN_STA_AMPDU_DEF_RXWINSIZE 123 #if defined(SD9177) && !defined(COEX_APP_SUPPORT) 124 #define MLAN_STA_AMPDU_DEF_RXWINSIZE 64 125 #else 126 #define MLAN_STA_AMPDU_DEF_RXWINSIZE 32 127 #endif 128 #endif 129 #endif /* STA_SUPPORT */ 130 131 #ifdef UAP_SUPPORT 132 /** Default Win size attached during ADDBA request */ 133 #ifndef MLAN_UAP_AMPDU_DEF_TXWINSIZE 134 #if defined(SD9177) && defined(COEX_APP_SUPPORT) 135 #define MLAN_UAP_AMPDU_DEF_TXWINSIZE 32 136 #else 137 #define MLAN_UAP_AMPDU_DEF_TXWINSIZE 64 138 #endif 139 #endif 140 141 /** Default Win size attached during ADDBA response */ 142 #ifndef MLAN_UAP_AMPDU_DEF_RXWINSIZE 143 #if defined(SD9177) && !defined(COEX_APP_SUPPORT) 144 #define MLAN_UAP_AMPDU_DEF_RXWINSIZE 64 145 #else 146 #define MLAN_UAP_AMPDU_DEF_RXWINSIZE 32 147 #endif 148 #endif 149 150 #endif /* UAP_SUPPORT */ 151 152 /** Block ack timeout value */ 153 #define MLAN_DEFAULT_BLOCK_ACK_TIMEOUT 0U 154 /** Maximum Tx Win size configured for ADDBA request [10 bits] */ 155 #define MLAN_AMPDU_MAX_TXWINSIZE 0x3ff 156 /** Maximum Rx Win size configured for ADDBA request [10 bits] */ 157 #define MLAN_AMPDU_MAX_RXWINSIZE 0x3ff 158 159 /** Rate index for HR/DSSS 0 */ 160 #define MLAN_RATE_INDEX_HRDSSS0 0 161 /** Rate index for HR/DSSS 3 */ 162 #define MLAN_RATE_INDEX_HRDSSS3 3 163 /** Rate index for OFDM 0 */ 164 #define MLAN_RATE_INDEX_OFDM0 4U 165 /** Rate index for OFDM 7 */ 166 #define MLAN_RATE_INDEX_OFDM7 11 167 /** Rate index for MCS 0 */ 168 #define MLAN_RATE_INDEX_MCS0 0U 169 /** Rate index for MCS 2 */ 170 #define MLAN_RATE_INDEX_MCS2 2U 171 /** Rate index for MCS 4 */ 172 #define MLAN_RATE_INDEX_MCS4 4U 173 /** Rate index for MCS 7 */ 174 #define MLAN_RATE_INDEX_MCS7 7U 175 /** Rate index for MCS 8 */ 176 #define MLAN_RATE_INDEX_MCS8 8U 177 /** Rate index for MCS 9 */ 178 #define MLAN_RATE_INDEX_MCS9 9U 179 #if CONFIG_11AX 180 /** Rate index for MCS11 */ 181 #define MLAN_RATE_INDEX_MCS11 11U 182 #endif 183 /** Rate index for MCS 32 */ 184 #define MLAN_RATE_INDEX_MCS32 32U 185 /** Rate index for MCS 127 */ 186 #define MLAN_RATE_INDEX_MCS127 127U 187 #if (CONFIG_11AC) || (CONFIG_11AX) 188 #define MLAN_RATE_NSS1 1 189 #define MLAN_RATE_NSS2 2 190 #endif 191 192 /** Rate bitmap for OFDM 0 */ 193 #define MLAN_RATE_BITMAP_OFDM0 16 194 /** Rate bitmap for OFDM 7 */ 195 #define MLAN_RATE_BITMAP_OFDM7 23 196 /** Rate bitmap for MCS 0 */ 197 #define MLAN_RATE_BITMAP_MCS0 32U 198 /** Rate bitmap for MCS 127 */ 199 #define MLAN_RATE_BITMAP_MCS127 159 200 #if CONFIG_11AC 201 #define MLAN_RATE_BITMAP_NSS1_MCS0 160 202 #define MLAN_RATE_BITMAP_NSS1_MCS9 169 203 #define MLAN_RATE_BITMAP_NSS2_MCS0 176 204 #define MLAN_RATE_BITMAP_NSS2_MCS9 185 205 #endif 206 207 /** MU beamformer */ 208 #define DEFALUT_11AC_CAP_BEAMFORMING_RESET_MASK (MBIT(19)) 209 #ifdef RW610 210 /** Short GI for 80MHz/TVHT_MODE_4C */ 211 #define DEFALUT_11AC_CAP_SHORTGI_80MHZ_RESET_MASK (MBIT(5)) 212 /** HE Phy Cap Info(40MHz in 2.4GHz band) */ 213 #define DEFAULT_11AX_CAP_40MHZIH2_4GHZBAND_RESET_MASK (MBIT(1)) 214 #endif 215 216 /** Size of rx data buffer */ 217 #define MLAN_RX_DATA_BUF_SIZE (4 * 1024) 218 /** Size of rx command buffer */ 219 #define MLAN_RX_CMD_BUF_SIZE (2 * 1024) 220 221 /** MLAN MAC Address Length */ 222 #define MLAN_MAC_ADDR_LENGTH (6U) 223 /** MLAN 802.11 MAC Address */ 224 typedef t_u8 mlan_802_11_mac_addr[MLAN_MAC_ADDR_LENGTH]; 225 226 /** MLAN Maximum SSID Length */ 227 #define MLAN_MAX_SSID_LENGTH (32U) 228 229 /** RTS/FRAG related defines */ 230 /** Minimum RTS value */ 231 #define MLAN_RTS_MIN_VALUE (0) 232 /** Maximum RTS value */ 233 #define MLAN_RTS_MAX_VALUE (2347) 234 /** Minimum FRAG value */ 235 #define MLAN_FRAG_MIN_VALUE (256) 236 /** Maximum FRAG value */ 237 #define MLAN_FRAG_MAX_VALUE (2346) 238 239 /** Minimum tx retry count */ 240 #define MLAN_TX_RETRY_MIN (0) 241 /** Maximum tx retry count */ 242 #define MLAN_TX_RETRY_MAX (14) 243 244 /** define SDIO block size for data Tx/Rx */ 245 /* We support up to 480-byte block size due to FW buffer limitation. */ 246 #define MLAN_SDIO_BLOCK_SIZE 256U 247 248 /** define SDIO block size for firmware download */ 249 #define MLAN_SDIO_BLOCK_SIZE_FW_DNLD MLAN_SDIO_BLOCK_SIZE 250 251 /** define allocated buffer size */ 252 #define ALLOC_BUF_SIZE (4 * 1024) 253 254 /** SDIO IO Port mask */ 255 #define MLAN_SDIO_IO_PORT_MASK 0xfffff 256 /** SDIO Block/Byte mode mask */ 257 #define MLAN_SDIO_BYTE_MODE_MASK 0x80000000U 258 259 /** Max retry number of IO write */ 260 #define MAX_READ_IOMEM_RETRY 2 261 262 /** IN parameter */ 263 #define IN 264 /** OUT parameter */ 265 #define OUT 266 267 /** BIT value */ 268 #define MBIT(x) (((t_u32)1) << (x)) 269 270 #define MRVL_PKT_TYPE_MGMT_FRAME 0xE5 271 272 /** Buffer flag for requeued packet */ 273 #define MLAN_BUF_FLAG_REQUEUED_PKT MBIT(0) 274 /** Buffer flag for transmit buf from moal */ 275 #define MLAN_BUF_FLAG_MOAL_TX_BUF MBIT(1) 276 /** Buffer flag for malloc mlan_buffer */ 277 #define MLAN_BUF_FLAG_MALLOC_BUF MBIT(2) 278 279 /** Buffer flag for bridge packet */ 280 #define MLAN_BUF_FLAG_BRIDGE_BUF MBIT(3) 281 282 /** Buffer flag for TX_STATUS */ 283 #define MLAN_BUF_FLAG_TX_STATUS MBIT(10) 284 285 #ifdef DEBUG_LEVEL1 286 /** Debug level bit definition */ 287 #define MMSG MBIT(0) 288 #define MFATAL MBIT(1) 289 #define MERROR MBIT(2) 290 #define MDATA MBIT(3) 291 #define MCMND MBIT(4) 292 #define MEVENT MBIT(5) 293 #define MINTR MBIT(6) 294 #define MIOCTL MBIT(7) 295 296 #define MDAT_D MBIT(16) 297 #define MCMD_D MBIT(17) 298 #define MEVT_D MBIT(18) 299 #define MFW_D MBIT(19) 300 #define MIF_D MBIT(20) 301 302 #define MENTRY MBIT(28) 303 #define MWARN MBIT(29) 304 #define MINFO MBIT(30) 305 #define MHEX_DUMP MBIT(31) 306 #endif /* DEBUG_LEVEL1 */ 307 308 /** Memory allocation type: DMA */ 309 #define MLAN_MEM_DMA MBIT(0U) 310 311 /** Default memory allocation flag */ 312 #define MLAN_MEM_DEF 0U 313 314 #if CONFIG_WIFI_IND_DNLD 315 /** driver initial the fw reset */ 316 #define FW_RELOAD_SDIO_INBAND_RESET 1 317 /** out band reset trigger reset, no interface re-emulation */ 318 #define FW_RELOAD_NO_EMULATION 2 319 /** out band reset with interface re-emulation */ 320 #define FW_RELOAD_WITH_EMULATION 3 321 /** sdio hw reset */ 322 #define FW_RELOAD_SDIO_HW_RESET 5 323 #endif 324 325 /** MrvlExtIEtypesHeader_t */ 326 typedef MLAN_PACK_START struct _MrvlExtIEtypesHeader 327 { 328 /** Header type */ 329 t_u16 type; 330 /** Header length */ 331 t_u16 len; 332 /** ext id */ 333 t_u8 ext_id; 334 } MLAN_PACK_END MrvlExtIEtypesHeader_t; 335 336 /** MrvlIEtypes_Data_t */ 337 typedef MLAN_PACK_START struct _MrvlExtIEtypes_Data_t 338 { 339 /** Header */ 340 MrvlExtIEtypesHeader_t header; 341 /** Data */ 342 t_u8 data[]; 343 } MLAN_PACK_END MrvlExtIEtypes_Data_t; 344 345 /** mlan_status */ 346 typedef enum _mlan_status 347 { 348 MLAN_STATUS_FAILURE = 0xffffffff, 349 MLAN_STATUS_SUCCESS = 0, 350 MLAN_STATUS_PENDING, 351 MLAN_STATUS_RESOURCE, 352 } mlan_status; 353 354 /** mlan_error_code */ 355 typedef enum _mlan_error_code 356 { 357 /** No error */ 358 MLAN_ERROR_NO_ERROR = 0, 359 /** Firmware/device errors below (MSB=0) */ 360 MLAN_ERROR_FW_NOT_READY = 0x00000001, 361 MLAN_ERROR_FW_BUSY, 362 MLAN_ERROR_FW_CMDRESP, 363 MLAN_ERROR_DATA_TX_FAIL, 364 MLAN_ERROR_DATA_RX_FAIL, 365 /** Driver errors below (MSB=1) */ 366 MLAN_ERROR_PKT_SIZE_INVALID = 0x80000001, 367 MLAN_ERROR_PKT_TIMEOUT, 368 MLAN_ERROR_PKT_INVALID, 369 MLAN_ERROR_CMD_INVALID, 370 MLAN_ERROR_CMD_TIMEOUT, 371 MLAN_ERROR_CMD_DNLD_FAIL, 372 MLAN_ERROR_CMD_CANCEL, 373 MLAN_ERROR_CMD_RESP_FAIL, 374 MLAN_ERROR_CMD_ASSOC_FAIL, 375 MLAN_ERROR_CMD_SCAN_FAIL, 376 MLAN_ERROR_IOCTL_INVALID, 377 MLAN_ERROR_IOCTL_FAIL, 378 MLAN_ERROR_EVENT_UNKNOWN, 379 MLAN_ERROR_INVALID_PARAMETER, 380 MLAN_ERROR_NO_MEM, 381 /** More to add */ 382 } mlan_error_code; 383 384 /** mlan_buf_type */ 385 typedef enum _mlan_buf_type 386 { 387 MLAN_BUF_TYPE_CMD = 1, 388 MLAN_BUF_TYPE_DATA, 389 MLAN_BUF_TYPE_EVENT, 390 MLAN_BUF_TYPE_RAW_DATA, 391 } mlan_buf_type; 392 393 /** MLAN BSS type */ 394 typedef enum _mlan_bss_type 395 { 396 MLAN_BSS_TYPE_STA = 0, 397 MLAN_BSS_TYPE_UAP = 1, 398 /* fixme: This macro will be enabled when 399 * mlan is completely integrated with wlan 400 */ 401 /* #ifdef WIFI_DIRECT_SUPPORT*/ 402 MLAN_BSS_TYPE_WIFIDIRECT = 2, 403 /*#endif*/ 404 MLAN_BSS_TYPE_ANY = 0xff, 405 } mlan_bss_type; 406 407 /** MLAN BSS role */ 408 typedef enum _mlan_bss_role 409 { 410 MLAN_BSS_ROLE_STA = 0, 411 MLAN_BSS_ROLE_UAP = 1, 412 MLAN_BSS_ROLE_ANY = 0xff, 413 } mlan_bss_role; 414 415 /** BSS role bit mask */ 416 #define BSS_ROLE_BIT_MASK MBIT(0) 417 418 /** Get BSS role */ 419 #define GET_BSS_ROLE(priv) ((unsigned)(priv)->bss_role & (BSS_ROLE_BIT_MASK)) 420 421 /** mlan_data_frame_type */ 422 typedef enum _mlan_data_frame_type 423 { 424 MLAN_DATA_FRAME_TYPE_ETH_II = 0, 425 MLAN_DATA_FRAME_TYPE_802_11, 426 } mlan_data_frame_type; 427 428 /** mlan_event_id */ 429 typedef enum _mlan_event_id 430 { 431 /* Event generated by firmware (MSB=0) */ 432 MLAN_EVENT_ID_FW_UNKNOWN = 0x00000001, 433 MLAN_EVENT_ID_FW_ADHOC_LINK_SENSED, 434 MLAN_EVENT_ID_FW_ADHOC_LINK_LOST, 435 MLAN_EVENT_ID_FW_DISCONNECTED, 436 MLAN_EVENT_ID_FW_MIC_ERR_UNI, 437 MLAN_EVENT_ID_FW_MIC_ERR_MUL, 438 MLAN_EVENT_ID_FW_BCN_RSSI_LOW, 439 MLAN_EVENT_ID_FW_BCN_RSSI_HIGH, 440 MLAN_EVENT_ID_FW_BCN_SNR_LOW, 441 MLAN_EVENT_ID_FW_BCN_SNR_HIGH, 442 MLAN_EVENT_ID_FW_MAX_FAIL, 443 MLAN_EVENT_ID_FW_DATA_RSSI_LOW, 444 MLAN_EVENT_ID_FW_DATA_RSSI_HIGH, 445 MLAN_EVENT_ID_FW_DATA_SNR_LOW, 446 MLAN_EVENT_ID_FW_DATA_SNR_HIGH, 447 MLAN_EVENT_ID_FW_LINK_QUALITY, 448 MLAN_EVENT_ID_FW_PORT_RELEASE, 449 MLAN_EVENT_ID_FW_PRE_BCN_LOST, 450 MLAN_EVENT_ID_FW_WMM_CONFIG_CHANGE, 451 MLAN_EVENT_ID_FW_HS_WAKEUP, 452 MLAN_EVENT_ID_FW_BG_SCAN, 453 MLAN_EVENT_ID_FW_WEP_ICV_ERR, 454 MLAN_EVENT_ID_FW_STOP_TX, 455 MLAN_EVENT_ID_FW_START_TX, 456 MLAN_EVENT_ID_FW_CHANNEL_SWITCH_ANN, 457 MLAN_EVENT_ID_FW_RADAR_DETECTED, 458 MLAN_EVENT_ID_FW_CHANNEL_REPORT_RDY, 459 MLAN_EVENT_ID_FW_BW_CHANGED, 460 #ifdef WIFI_DIRECT_SUPPORT 461 MLAN_EVENT_ID_FW_REMAIN_ON_CHAN_EXPIRED, 462 #endif 463 #ifdef UAP_SUPPORT 464 MLAN_EVENT_ID_UAP_FW_BSS_START, 465 MLAN_EVENT_ID_UAP_FW_BSS_ACTIVE, 466 MLAN_EVENT_ID_UAP_FW_BSS_IDLE, 467 MLAN_EVENT_ID_UAP_FW_STA_CONNECT, 468 MLAN_EVENT_ID_UAP_FW_STA_DISCONNECT, 469 #endif 470 471 /* Event generated by MLAN driver (MSB=1) */ 472 MLAN_EVENT_ID_DRV_CONNECTED = 0x80000001, 473 MLAN_EVENT_ID_DRV_DEFER_HANDLING, 474 MLAN_EVENT_ID_DRV_HS_ACTIVATED, 475 MLAN_EVENT_ID_DRV_HS_DEACTIVATED, 476 MLAN_EVENT_ID_DRV_MGMT_FRAME, 477 MLAN_EVENT_ID_DRV_OBSS_SCAN_PARAM, 478 MLAN_EVENT_ID_DRV_PASSTHRU, 479 MLAN_EVENT_ID_DRV_SCAN_REPORT, 480 MLAN_EVENT_ID_DRV_MEAS_REPORT, 481 MLAN_EVENT_ID_DRV_ASSOC_FAILURE_REPORT, 482 MLAN_EVENT_ID_DRV_REPORT_STRING, 483 MLAN_EVENT_ID_DRV_DBG_DUMP, 484 } mlan_event_id; 485 486 /** Data Structures */ 487 /** mlan_image data structure */ 488 typedef struct _mlan_fw_image 489 { 490 /** Helper image buffer pointer */ 491 t_u8 *phelper_buf; 492 /** Helper image length */ 493 t_u32 helper_len; 494 /** Firmware image buffer pointer */ 495 t_u8 *pfw_buf; 496 /** Firmware image length */ 497 t_u32 fw_len; 498 #if CONFIG_WIFI_IND_DNLD 499 /** Firmware reload flag */ 500 t_u8 fw_reload; 501 #endif 502 } mlan_fw_image, *pmlan_fw_image; 503 504 /** Custom data structure */ 505 typedef struct _mlan_init_param 506 { 507 /** Cal data buffer pointer */ 508 t_u8 *pcal_data_buf; 509 /** Cal data length */ 510 t_u32 cal_data_len; 511 /** Other custom data */ 512 } mlan_init_param, *pmlan_init_param; 513 514 /** Channel usability flags */ 515 #define NXP_CHANNEL_NO_OFDM MBIT(9) 516 #define NXP_CHANNEL_NO_CCK MBIT(8) 517 #define NXP_CHANNEL_DISABLED MBIT(7) 518 /* BIT 5/6 resevered for FW */ 519 #define NXP_CHANNEL_NOHT160 MBIT(4) 520 #define NXP_CHANNEL_NOHT80 MBIT(3) 521 #define NXP_CHANNEL_NOHT40 MBIT(2) 522 #define NXP_CHANNEL_DFS MBIT(1) 523 #define NXP_CHANNEL_PASSIVE MBIT(0) 524 525 /** CFP dynamic (non-const) elements */ 526 typedef struct _cfp_dyn_t 527 { 528 /** extra flags to specify channel usability 529 * bit 9 : if set, channel is non-OFDM 530 * bit 8 : if set, channel is non-CCK 531 * bit 7 : if set, channel is disabled 532 * bit 5/6 resevered for FW 533 * bit 4 : if set, 160MHz on channel is disabled 534 * bit 3 : if set, 80MHz on channel is disabled 535 * bit 2 : if set, 40MHz on channel is disabled 536 * bit 1 : if set, channel is DFS channel 537 * bit 0 : if set, channel is passive 538 */ 539 t_u16 flags; 540 /** TRUE: Channel is blacklisted (do not use) */ 541 t_bool blacklist; 542 } cfp_dyn_t; 543 544 /** Chan-Freq-TxPower mapping table*/ 545 typedef struct _chan_freq_power_t 546 { 547 /** Channel Number */ 548 t_u16 channel; 549 /** Frequency of this Channel */ 550 t_u32 freq; 551 /** Max allowed Tx power level */ 552 t_u16 max_tx_power; 553 /** TRUE:radar detect required for BAND A or passive scan for BAND B/G; 554 * FALSE:radar detect not required for BAND A or active scan for BAND B/G*/ 555 t_bool passive_scan_or_radar_detect; 556 /** Elements associated to cfp that change at run-time */ 557 cfp_dyn_t dynamic; 558 } chan_freq_power_t; 559 560 /** mlan_event data structure */ 561 typedef struct _mlan_event 562 { 563 /** BSS index number for multiple BSS support */ 564 t_u32 bss_index; 565 /** Event ID */ 566 mlan_event_id event_id; 567 /** Event length */ 568 t_u32 event_len; 569 /** Event buffer */ 570 t_u8 event_buf[1]; 571 } mlan_event, *pmlan_event; 572 573 #if CONFIG_P2P 574 /** mlan_event data structure */ 575 typedef struct _mlan_event_p2p 576 { 577 /** Event length */ 578 t_u32 event_len; 579 /** Event buffer */ 580 t_u8 event_buf[0]; 581 } mlan_event_p2p, *pmlan_event_p2p; 582 #endif 583 584 #if CONFIG_EXT_SCAN_SUPPORT 585 /** mlan_event_scan_result data structure */ 586 typedef MLAN_PACK_START struct _mlan_event_scan_result 587 { 588 /** Event ID */ 589 t_u16 event_id; 590 /** BSS index number for multiple BSS support */ 591 t_u8 bss_index; 592 /** BSS type */ 593 t_u8 bss_type; 594 /** More event available or not */ 595 t_u8 more_event; 596 /** Reserved */ 597 t_u8 reserved[3]; 598 /** Size of the response buffer */ 599 t_u16 buf_size; 600 /** Number of BSS in scan response */ 601 t_u8 num_of_set; 602 } MLAN_PACK_END mlan_event_scan_result, *pmlan_event_scan_result; 603 #endif 604 605 /** mlan_buffer data structure */ 606 typedef struct _mlan_buffer 607 { 608 /** Pointer to previous mlan_buffer */ 609 // struct _mlan_buffer *pprev; 610 /** Pointer to next mlan_buffer */ 611 // struct _mlan_buffer *pnext; 612 /** Status code from firmware/driver */ 613 t_u32 status_code; 614 /** Flags for this buffer */ 615 t_u32 flags; 616 /** BSS index number for multiple BSS support */ 617 t_u32 bss_index; 618 /** Buffer descriptor, e.g. skb in Linux */ 619 t_void *pdesc; 620 /** Private member added for WMSDK. This is used to store the lwip pbuf 621 pointer */ 622 t_void *lwip_pbuf; 623 /** Pointer to buffer */ 624 t_u8 *pbuf; 625 /** Offset to data */ 626 t_u32 data_offset; 627 /** Data length */ 628 t_u32 data_len; 629 /** Buffer type: data, cmd, event etc. */ 630 mlan_buf_type buf_type; 631 632 /** Fields below are valid for data packet only */ 633 /** QoS priority */ 634 t_u32 priority; 635 /** Time stamp when packet is received (seconds) */ 636 // t_u32 in_ts_sec; 637 /** Time stamp when packet is received (micro seconds) */ 638 // t_u32 in_ts_usec; 639 /** Time stamp when packet is processed (seconds) */ 640 // t_u32 out_ts_sec; 641 /** Time stamp when packet is processed (micro seconds) */ 642 // t_u32 out_ts_usec; 643 644 /** Fields below are valid for MLAN module only */ 645 /** Pointer to parent mlan_buffer */ 646 // struct _mlan_buffer *pparent; 647 /** Use count for this buffer */ 648 t_u32 use_count; 649 } mlan_buffer, *pmlan_buffer; 650 651 /** mlan_bss_attr data structure */ 652 typedef struct _mlan_bss_attr 653 { 654 /** BSS type */ 655 mlan_bss_type bss_type; 656 /** Data frame type: Ethernet II, 802.11, etc. */ 657 t_u32 frame_type; 658 /** The BSS is active (non-0) or not (0). */ 659 t_u32 active; 660 /** BSS Priority */ 661 t_u32 bss_priority; 662 /** BSS number */ 663 t_u32 bss_num; 664 } mlan_bss_attr, *pmlan_bss_attr; 665 666 #ifdef PRAGMA_PACK 667 #pragma pack(push, 1) 668 #endif 669 670 /** Type enumeration for the command result */ 671 typedef MLAN_PACK_START enum _mlan_cmd_result_e { 672 MLAN_CMD_RESULT_SUCCESS = 0, 673 MLAN_CMD_RESULT_FAILURE = 1, 674 MLAN_CMD_RESULT_TIMEOUT = 2, 675 MLAN_CMD_RESULT_INVALID_DATA = 3 676 } MLAN_PACK_END mlan_cmd_result_e; 677 678 #define WMM_AC_BK 0 679 #define WMM_AC_BE 1 680 #define WMM_AC_VI 2 681 #define WMM_AC_VO 3 682 683 typedef t_u8 mlan_wmm_ac_e; 684 685 /** Type enumeration for the action field in the Queue Config command */ 686 typedef MLAN_PACK_START enum _mlan_wmm_queue_config_action_e { 687 MLAN_WMM_QUEUE_CONFIG_ACTION_GET = 0, 688 MLAN_WMM_QUEUE_CONFIG_ACTION_SET = 1, 689 MLAN_WMM_QUEUE_CONFIG_ACTION_DEFAULT = 2, 690 MLAN_WMM_QUEUE_CONFIG_ACTION_MAX 691 } MLAN_PACK_END mlan_wmm_queue_config_action_e; 692 693 /** Type enumeration for the action field in the queue stats command */ 694 typedef MLAN_PACK_START enum _mlan_wmm_queue_stats_action_e { 695 MLAN_WMM_STATS_ACTION_START = 0, 696 MLAN_WMM_STATS_ACTION_STOP = 1, 697 MLAN_WMM_STATS_ACTION_GET_CLR = 2, 698 MLAN_WMM_STATS_ACTION_SET_CFG = 3, /* Not currently used */ 699 MLAN_WMM_STATS_ACTION_GET_CFG = 4, /* Not currently used */ 700 MLAN_WMM_STATS_ACTION_MAX 701 } MLAN_PACK_END mlan_wmm_queue_stats_action_e; 702 703 /** 704 * @brief IOCTL structure for a Traffic stream status. 705 * 706 */ 707 typedef MLAN_PACK_START struct 708 { 709 /** TSID: Range: 0->7 */ 710 t_u8 tid; 711 /** TSID specified is valid */ 712 t_u8 valid; 713 /** AC TSID is active on */ 714 t_u8 access_category; 715 /** UP specified for the TSID */ 716 t_u8 user_priority; 717 /** Power save mode for TSID: 0 (legacy), 1 (UAPSD) */ 718 t_u8 psb; 719 /** Upstream(0), Downlink(1), Bidirectional(3) */ 720 t_u8 flow_dir; 721 /** Medium time granted for the TSID */ 722 t_u16 medium_time; 723 } MLAN_PACK_END wlan_ioctl_wmm_ts_status_t, 724 /** Type definition of mlan_ds_wmm_ts_status for MLAN_OID_WMM_CFG_TS_STATUS */ 725 mlan_ds_wmm_ts_status, *pmlan_ds_wmm_ts_status; 726 727 /** Max Ie length */ 728 #define MAX_IE_SIZE 256U 729 730 /** custom IE */ 731 typedef MLAN_PACK_START struct _custom_ie 732 { 733 /** IE Index */ 734 t_u16 ie_index; 735 /** Mgmt Subtype Mask */ 736 t_u16 mgmt_subtype_mask; 737 /** IE Length */ 738 t_u16 ie_length; 739 /** IE buffer */ 740 t_u8 ie_buffer[MAX_IE_SIZE]; 741 } MLAN_PACK_END custom_ie; 742 743 /** TLV buffer : custom IE */ 744 typedef MLAN_PACK_START struct _tlvbuf_custom_ie 745 { 746 /** Tag */ 747 t_u16 type; 748 /** Length */ 749 t_u16 length; 750 /** custom IE data */ 751 custom_ie ie_data[0]; 752 } MLAN_PACK_END tlvbuf_custom_ie; 753 754 /** Max IE index to FW */ 755 #define MAX_MGMT_IE_INDEX_TO_FW 4U 756 /** Max IE index per BSS */ 757 #define MAX_MGMT_IE_INDEX 16 758 759 /** custom IE info */ 760 typedef MLAN_PACK_START struct _custom_ie_info 761 { 762 /** size of buffer */ 763 t_u16 buf_size; 764 /** no of buffers of buf_size */ 765 t_u16 buf_count; 766 } MLAN_PACK_END custom_ie_info; 767 768 /** TLV buffer : Max Mgmt IE */ 769 typedef MLAN_PACK_START struct _tlvbuf_max_mgmt_ie 770 { 771 /** Type */ 772 t_u16 type; 773 /** Length */ 774 t_u16 len; 775 /** No of tuples */ 776 t_u16 count; 777 /** custom IE info tuples */ 778 custom_ie_info info[MAX_MGMT_IE_INDEX]; 779 } MLAN_PACK_END tlvbuf_max_mgmt_ie; 780 781 /** TLV buffer : custom IE */ 782 typedef MLAN_PACK_START struct _mlan_ds_misc_custom_ie 783 { 784 /** Type */ 785 t_u16 type; 786 /** Length */ 787 t_u16 len; 788 /** IE data */ 789 custom_ie ie_data_list[MAX_MGMT_IE_INDEX_TO_FW]; 790 /** Max mgmt IE TLV */ 791 tlvbuf_max_mgmt_ie max_mgmt_ie; 792 } MLAN_PACK_END mlan_ds_misc_custom_ie; 793 794 /** channel type */ 795 enum mlan_channel_type 796 { 797 CHAN_NO_HT, 798 CHAN_HT20, 799 CHAN_HT40MINUS, 800 CHAN_HT40PLUS, 801 CHAN_VHT80 802 }; 803 804 /** channel band */ 805 enum 806 { 807 BAND_2GHZ = 0, 808 BAND_5GHZ = 1, 809 BAND_6GHZ = 2, 810 BAND_4GHZ = 3, 811 }; 812 813 /** Band_Config_t */ 814 typedef MLAN_PACK_START struct _Band_Config_t 815 { 816 #ifdef BIG_ENDIAN_SUPPORT 817 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=user*/ 818 t_u8 scanMode : 2; 819 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 820 t_u8 chan2Offset : 2; 821 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 822 t_u8 chanWidth : 2; 823 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 824 t_u8 chanBand : 2; 825 #else 826 /** Band Info - (00)=2.4GHz, (01)=5GHz */ 827 t_u8 chanBand : 2; 828 /** Channel Width - (00)=20MHz, (10)=40MHz, (11)=80MHz */ 829 t_u8 chanWidth : 2; 830 /** Secondary Channel Offset - (00)=None, (01)=Above, (11)=Below */ 831 t_u8 chan2Offset : 2; 832 /** Channel Selection Mode - (00)=manual, (01)=ACS, (02)=Adoption mode*/ 833 t_u8 scanMode : 2; 834 #endif 835 } MLAN_PACK_END Band_Config_t; 836 837 /** channel_band_t */ 838 typedef MLAN_PACK_START struct _chan_band_info 839 { 840 /** Band Configuration */ 841 Band_Config_t bandcfg; 842 /** channel */ 843 t_u8 channel; 844 /** 11n flag */ 845 t_u8 is_11n_enabled; 846 /** center channel */ 847 t_u8 center_chan; 848 #if defined(ENABLE_802_11H) && defined(DFS_SUPPORT) 849 /** dfs channel flag */ 850 t_u8 is_dfs_chan; 851 #endif 852 } MLAN_PACK_END chan_band_info; 853 854 /** csi event data structure */ 855 #if CONFIG_CSI 856 typedef MLAN_PACK_START struct _csi_record_ds 857 { 858 /** Length in DWORDS, including header */ 859 t_u16 Len; 860 /** CSI signature. 0xABCD fixed */ 861 t_u16 CSI_Sign; 862 /** User defined HeaderID */ 863 t_u32 CSI_HeaderID; 864 /** Packet info field */ 865 t_u16 PKT_info; 866 /** Frame control field for the received packet*/ 867 t_u16 FCF; 868 /** Timestamp when packet received */ 869 t_u64 TSF; 870 /** Received Packet Destination MAC Address */ 871 t_u8 Dst_MAC[6]; 872 /** Received Packet Source MAC Address */ 873 t_u8 Src_MAC[6]; 874 /** RSSI for antenna A */ 875 t_u8 Rx_RSSI_A; 876 /** RSSI for antenna B */ 877 t_u8 Rx_RSSI_B; 878 /** Noise floor for antenna A */ 879 t_u8 Rx_NF_A; 880 /** Noise floor for antenna A */ 881 t_u8 Rx_NF_B; 882 /** Rx signal strength above noise floor */ 883 t_u8 Rx_SINR; 884 /** Channel */ 885 t_u8 channel; 886 /** user defined Chip ID */ 887 t_u16 chip_id; 888 /** Reserved */ 889 t_u32 rsvd; 890 /** CSI data length in DWORDs */ 891 t_u32 CSI_Data_Length; 892 /** Start of CSI data */ 893 t_u8 CSI_Data[0]; 894 /** At the end of CSI raw data, user defined TailID of 4 bytes*/ 895 } MLAN_PACK_END csi_record_ds, *pcsi_record_ds; 896 #endif 897 898 #ifdef PRAGMA_PACK 899 #pragma pack(pop) 900 #endif 901 902 /** mlan_callbacks data structure */ 903 typedef struct _mlan_callbacks 904 { 905 #if 0 906 /** moal_get_fw_data */ 907 mlan_status(*moal_get_fw_data) (IN t_void * pmoal_handle, 908 IN t_u32 offset, 909 IN t_u32 len, OUT t_u8 * pbuf); 910 /** moal_init_fw_complete */ 911 mlan_status(*moal_init_fw_complete) (IN t_void * pmoal_handle, 912 IN mlan_status status); 913 /** moal_shutdown_fw_complete */ 914 mlan_status(*moal_shutdown_fw_complete) (IN t_void * pmoal_handle, 915 IN mlan_status status); 916 /** moal_send_packet_complete */ 917 mlan_status(*moal_send_packet_complete) (IN t_void * pmoal_handle, 918 IN pmlan_buffer pmbuf, 919 IN mlan_status status); 920 /** moal_recv_complete */ 921 mlan_status(*moal_recv_complete) (IN t_void * pmoal_handle, 922 IN pmlan_buffer pmbuf, 923 IN t_u32 port, IN mlan_status status); 924 #endif /* 0 */ 925 /** moal_recv_packet */ 926 mlan_status (*moal_recv_packet)(IN t_void *pmoal_handle, IN pmlan_buffer pmbuf); 927 #if 0 928 /** moal_recv_event */ 929 mlan_status(*moal_recv_event) (IN t_void * pmoal_handle, 930 IN pmlan_event pmevent); 931 /** moal_ioctl_complete */ 932 mlan_status(*moal_ioctl_complete) (IN t_void * pmoal_handle, 933 IN pmlan_ioctl_req pioctl_req, 934 IN mlan_status status); 935 /** moal_alloc_mlan_buffer */ 936 mlan_status(*moal_alloc_mlan_buffer) (IN t_void * pmoal_handle, 937 IN t_u32 size, 938 OUT pmlan_buffer * pmbuf); 939 /** moal_free_mlan_buffer */ 940 mlan_status(*moal_free_mlan_buffer) (IN t_void * pmoal_handle, 941 IN pmlan_buffer pmbuf); 942 /** moal_write_reg */ 943 mlan_status(*moal_write_reg) (IN t_void * pmoal_handle, 944 IN t_u32 reg, IN t_u32 data); 945 /** moal_read_reg */ 946 mlan_status(*moal_read_reg) (IN t_void * pmoal_handle, 947 IN t_u32 reg, OUT t_u32 * data); 948 /** moal_write_data_sync */ 949 mlan_status(*moal_write_data_sync) (IN t_void * pmoal_handle, 950 IN pmlan_buffer pmbuf, 951 IN t_u32 port, IN t_u32 timeout); 952 /** moal_read_data_sync */ 953 mlan_status(*moal_read_data_sync) (IN t_void * pmoal_handle, 954 IN OUT pmlan_buffer pmbuf, 955 IN t_u32 port, IN t_u32 timeout); 956 #endif /* 0 */ 957 /** moal_malloc */ 958 mlan_status (*moal_malloc)(IN t_void *pmoal_handle, IN t_u32 size, IN t_u32 flag, OUT t_u8 **ppbuf); 959 /** moal_mfree */ 960 mlan_status (*moal_mfree)(IN t_void *pmoal_handle, IN t_u8 *pbuf); 961 #if 0 962 /** moal_memset */ 963 t_void *(*moal_memset) (IN t_void * pmoal_handle, 964 IN t_void * pmem, IN t_u8 byte, IN t_u32 num); 965 /** moal_memcpy */ 966 t_void *(*moal_memcpy) (IN t_void * pmoal_handle, 967 IN t_void * pdest, 968 IN const t_void * psrc, IN t_u32 num); 969 /** moal_memmove */ 970 t_void *(*moal_memmove) (IN t_void * pmoal_handle, 971 IN t_void * pdest, 972 IN const t_void * psrc, IN t_u32 num); 973 /** moal_memcmp */ 974 t_s32(*moal_memcmp) (IN t_void * pmoal_handle, 975 IN const t_void * pmem1, 976 IN const t_void * pmem2, IN t_u32 num); 977 /** moal_udelay */ 978 t_void(*moal_udelay) (IN t_void * pmoal_handle, IN t_u32 udelay); 979 /** moal_get_system_time */ 980 mlan_status(*moal_get_system_time) (IN t_void * pmoal_handle, 981 OUT t_u32 * psec, OUT t_u32 * pusec); 982 #endif /* 0 */ 983 984 /** moal_memcpy_ext */ 985 t_void *(*moal_memcpy_ext)(t_void *pmoal, t_void *pdest, const t_void *psrc, t_u32 num, t_u32 dest_size); 986 987 /** moal_init_timer*/ 988 mlan_status (*moal_init_timer)(IN t_void *pmoal_handle, 989 OUT t_void *ptimer, 990 IN t_void (*callback)(osa_timer_arg_t arg), 991 IN t_void *pcontext); 992 /** moal_free_timer */ 993 mlan_status (*moal_free_timer)(IN t_void *pmoal_handle, IN t_void *ptimer); 994 /** moal_start_timer*/ 995 mlan_status (*moal_start_timer)(IN t_void *pmoal_handle, IN t_void *ptimer, IN bool periodic, IN t_u32 msec); 996 /** moal_reset_timer*/ 997 mlan_status (*moal_reset_timer)(IN t_void *pmoal_handle, IN t_void *ptimer); 998 /** moal_stop_timer*/ 999 mlan_status (*moal_stop_timer)(IN t_void *pmoal_handle, IN t_void *ptimer); 1000 /** moal_init_lock */ 1001 mlan_status (*moal_init_lock)(IN t_void *pmoal_handle, OUT t_void *plock); 1002 /** moal_free_lock */ 1003 mlan_status (*moal_free_lock)(IN t_void *pmoal_handle, IN t_void *plock); 1004 /** moal_spin_lock */ 1005 mlan_status (*moal_spin_lock)(IN t_void *pmoal_handle, IN t_void *plock); 1006 /** moal_spin_unlock */ 1007 mlan_status (*moal_spin_unlock)(IN t_void *pmoal_handle, IN t_void *plock); 1008 #if CONFIG_WMM 1009 /** moal_init_semaphore */ 1010 mlan_status (*moal_init_semaphore)(IN t_void *pmoal_handle, IN const char *name, OUT t_void *plock); 1011 /** moal_free_semaphore */ 1012 mlan_status (*moal_free_semaphore)(IN t_void *pmoal_handle, IN t_void *plock); 1013 /** moal_semaphore_get */ 1014 mlan_status (*moal_semaphore_get)(IN t_void *pmoal_handle, IN t_void *plock); 1015 /** moal_semaphore_put */ 1016 mlan_status (*moal_semaphore_put)(IN t_void *pmoal_handle, IN t_void *plock); 1017 #endif 1018 #if 0 1019 /** moal_print */ 1020 t_void(*moal_print) (IN t_void * pmoal_handle, 1021 IN t_u32 level, IN t_s8 * pformat, IN ...); 1022 /** moal_print_netintf */ 1023 t_void(*moal_print_netintf) (IN t_void * pmoal_handle, 1024 IN t_u32 bss_index, IN t_u32 level); 1025 /** moal_assert */ 1026 t_void(*moal_assert) (IN t_void * pmoal_handle, IN t_u32 cond); 1027 #endif /* 0 */ 1028 } mlan_callbacks, *pmlan_callbacks; 1029 1030 /** Interrupt Mode SDIO */ 1031 #define INT_MODE_SDIO 0 1032 /** Interrupt Mode GPIO */ 1033 #define INT_MODE_GPIO 1 1034 1035 /** Parameter unchanged, use MLAN default setting */ 1036 #define MLAN_INIT_PARA_UNCHANGED 0 1037 /** Parameter enabled, override MLAN default setting */ 1038 #define MLAN_INIT_PARA_ENABLED 1 1039 /** Parameter disabled, override MLAN default setting */ 1040 #define MLAN_INIT_PARA_DISABLED 2U 1041 1042 /** mlan_device data structure */ 1043 typedef struct _mlan_device 1044 { 1045 /** BSS Attributes */ 1046 mlan_bss_attr bss_attr[MLAN_MAX_BSS_NUM]; 1047 /** Callbacks */ 1048 mlan_callbacks callbacks; 1049 } mlan_device, *pmlan_device; 1050 1051 /** MLAN API function prototype */ 1052 #define MLAN_API 1053 1054 /** Registration */ 1055 MLAN_API mlan_status mlan_register(IN pmlan_device pmdevice, OUT t_void **ppmlan_adapter); 1056 1057 /** Un-registration */ 1058 MLAN_API mlan_status mlan_unregister(IN t_void *pmlan_adapter); 1059 1060 /** Firmware Initialization */ 1061 MLAN_API mlan_status mlan_init_fw(IN t_void *pmlan_adapter); 1062 #endif /* !_MLAN_DECL_H_ */ 1063
