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Searched refs:MIX_SR (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h19154 …__IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0xA0C… member
19200 #define GPC_PGC_MIX_SR_REG(base) ((base)->MIX_SR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h25335 __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h25335 __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h25335 __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h25335 __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h25335 __IO uint32_t MIX_SR; /**< GPC PGC Status Register, offset: 0x20C */ member