| /hal_nxp-latest/mcux/mcux-sdk/drivers/lpflexcomm/lpi2c/ |
| D | fsl_lpi2c.h | 730 *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; in LPI2C_MasterGetFifoCounts()
734 *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; in LPI2C_MasterGetFifoCounts()
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| D | fsl_lpi2c.c | 1318 … if ((xfer->direction == kLPI2C_Write) && ((base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) == 0U)) in LPI2C_RunTransferStateMachine()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lpi2c/ |
| D | fsl_lpi2c.h | 762 *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; in LPI2C_MasterGetFifoCounts()
766 *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; in LPI2C_MasterGetFifoCounts()
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| D | fsl_lpi2c.c | 1378 …if ((handle->transfer.direction == kLPI2C_Write) && ((base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) == 0U)) in LPI2C_TransferStateMachineWaitState()
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| D | S32K116_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| D | S32K118_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| D | S32K142W_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| D | S32K146_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| D | S32K142_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| D | S32K144W_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| D | S32K144_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_LPI2C.h | 92 __I uint32_t MFSR; /**< Master FIFO Status, offset: 0x5C */ member
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_LPI2C.h | 96 __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/ |
| D | MKE14Z4.h | 3531 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/ |
| D | MKE15Z4.h | 3532 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/ |
| D | MKE16Z4.h | 3530 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/ |
| D | MKE12Z7.h | 6359 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/ |
| D | MKE12Z9.h | 6253 __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/ |
| D | MKE17Z7.h | 6363 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/ |
| D | MKE13Z7.h | 6361 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/ |
| D | MKE14Z7.h | 6091 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/ |
| D | MKE17Z9.h | 6255 __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/ |
| D | MKE15Z7.h | 6093 __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/ |
| D | MKE13Z9.h | 6254 __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ member
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